894 lines
30 KiB
C
894 lines
30 KiB
C
#ifndef __iop_sw_mpu_defs_h
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#define __iop_sw_mpu_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
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* id: <not found>
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* last modfied: Mon Apr 11 16:10:19 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
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* id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope iop_sw_mpu */
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/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int cfg : 2;
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unsigned int dummy1 : 30;
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} reg_iop_sw_mpu_rw_sw_cfg_owner;
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#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
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#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
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/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int keep_owner : 1;
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unsigned int cmd : 2;
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unsigned int size : 3;
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unsigned int wr_spu0_mem : 1;
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unsigned int wr_spu1_mem : 1;
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unsigned int dummy1 : 24;
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} reg_iop_sw_mpu_rw_mc_ctrl;
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#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
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#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
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/* Register rw_mc_data, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int val : 32;
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} reg_iop_sw_mpu_rw_mc_data;
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#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
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#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
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/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
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typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
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#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
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#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
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/* Register rs_mc_data, scope iop_sw_mpu, type rs */
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typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
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#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
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/* Register r_mc_data, scope iop_sw_mpu, type r */
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typedef unsigned int reg_iop_sw_mpu_r_mc_data;
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#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
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/* Register r_mc_stat, scope iop_sw_mpu, type r */
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typedef struct {
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unsigned int busy_cpu : 1;
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unsigned int busy_mpu : 1;
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unsigned int busy_spu0 : 1;
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unsigned int busy_spu1 : 1;
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unsigned int owned_by_cpu : 1;
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unsigned int owned_by_mpu : 1;
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unsigned int owned_by_spu0 : 1;
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unsigned int owned_by_spu1 : 1;
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unsigned int dummy1 : 24;
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} reg_iop_sw_mpu_r_mc_stat;
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#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
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/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 8;
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unsigned int byte1 : 8;
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unsigned int byte2 : 8;
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unsigned int byte3 : 8;
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} reg_iop_sw_mpu_rw_bus0_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
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/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 8;
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unsigned int byte1 : 8;
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unsigned int byte2 : 8;
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unsigned int byte3 : 8;
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} reg_iop_sw_mpu_rw_bus0_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
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/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 1;
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unsigned int byte1 : 1;
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unsigned int byte2 : 1;
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unsigned int byte3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
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/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 1;
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unsigned int byte1 : 1;
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unsigned int byte2 : 1;
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unsigned int byte3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
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/* Register r_bus0_in, scope iop_sw_mpu, type r */
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typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
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#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
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/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 8;
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unsigned int byte1 : 8;
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unsigned int byte2 : 8;
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unsigned int byte3 : 8;
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} reg_iop_sw_mpu_rw_bus1_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
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/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 8;
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unsigned int byte1 : 8;
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unsigned int byte2 : 8;
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unsigned int byte3 : 8;
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} reg_iop_sw_mpu_rw_bus1_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
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/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 1;
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unsigned int byte1 : 1;
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unsigned int byte2 : 1;
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unsigned int byte3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
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/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int byte0 : 1;
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unsigned int byte1 : 1;
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unsigned int byte2 : 1;
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unsigned int byte3 : 1;
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unsigned int dummy1 : 28;
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} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
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#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
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/* Register r_bus1_in, scope iop_sw_mpu, type r */
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typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
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#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
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/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int val : 32;
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} reg_iop_sw_mpu_rw_gio_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
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#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
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/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int val : 32;
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} reg_iop_sw_mpu_rw_gio_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
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#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
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/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int val : 32;
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} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
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#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
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/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int val : 32;
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} reg_iop_sw_mpu_rw_gio_oe_set_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
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#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
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/* Register r_gio_in, scope iop_sw_mpu, type r */
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typedef unsigned int reg_iop_sw_mpu_r_gio_in;
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#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
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/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int intr0 : 1;
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unsigned int intr1 : 1;
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unsigned int intr2 : 1;
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unsigned int intr3 : 1;
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unsigned int intr4 : 1;
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unsigned int intr5 : 1;
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unsigned int intr6 : 1;
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unsigned int intr7 : 1;
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unsigned int intr8 : 1;
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unsigned int intr9 : 1;
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unsigned int intr10 : 1;
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unsigned int intr11 : 1;
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unsigned int intr12 : 1;
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unsigned int intr13 : 1;
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unsigned int intr14 : 1;
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unsigned int intr15 : 1;
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unsigned int intr16 : 1;
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unsigned int intr17 : 1;
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unsigned int intr18 : 1;
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unsigned int intr19 : 1;
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unsigned int intr20 : 1;
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unsigned int intr21 : 1;
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unsigned int intr22 : 1;
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unsigned int intr23 : 1;
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unsigned int intr24 : 1;
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unsigned int intr25 : 1;
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unsigned int intr26 : 1;
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unsigned int intr27 : 1;
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unsigned int intr28 : 1;
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unsigned int intr29 : 1;
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unsigned int intr30 : 1;
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unsigned int intr31 : 1;
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} reg_iop_sw_mpu_rw_cpu_intr;
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#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
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#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
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/* Register r_cpu_intr, scope iop_sw_mpu, type r */
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typedef struct {
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unsigned int intr0 : 1;
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unsigned int intr1 : 1;
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unsigned int intr2 : 1;
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unsigned int intr3 : 1;
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unsigned int intr4 : 1;
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unsigned int intr5 : 1;
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unsigned int intr6 : 1;
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unsigned int intr7 : 1;
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unsigned int intr8 : 1;
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unsigned int intr9 : 1;
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unsigned int intr10 : 1;
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unsigned int intr11 : 1;
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unsigned int intr12 : 1;
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unsigned int intr13 : 1;
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unsigned int intr14 : 1;
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unsigned int intr15 : 1;
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unsigned int intr16 : 1;
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unsigned int intr17 : 1;
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unsigned int intr18 : 1;
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unsigned int intr19 : 1;
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unsigned int intr20 : 1;
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unsigned int intr21 : 1;
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unsigned int intr22 : 1;
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unsigned int intr23 : 1;
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unsigned int intr24 : 1;
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unsigned int intr25 : 1;
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unsigned int intr26 : 1;
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unsigned int intr27 : 1;
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unsigned int intr28 : 1;
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unsigned int intr29 : 1;
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unsigned int intr30 : 1;
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unsigned int intr31 : 1;
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} reg_iop_sw_mpu_r_cpu_intr;
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#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
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/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int spu0_intr0 : 1;
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unsigned int spu1_intr0 : 1;
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unsigned int trigger_grp0 : 1;
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unsigned int trigger_grp4 : 1;
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unsigned int timer_grp0 : 1;
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unsigned int fifo_out0 : 1;
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unsigned int fifo_out0_extra : 1;
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unsigned int dmc_out0 : 1;
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unsigned int spu0_intr1 : 1;
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unsigned int spu1_intr1 : 1;
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unsigned int trigger_grp1 : 1;
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unsigned int trigger_grp5 : 1;
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unsigned int timer_grp1 : 1;
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unsigned int fifo_in0 : 1;
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unsigned int fifo_in0_extra : 1;
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unsigned int dmc_in0 : 1;
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unsigned int spu0_intr2 : 1;
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unsigned int spu1_intr2 : 1;
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unsigned int trigger_grp2 : 1;
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unsigned int trigger_grp6 : 1;
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unsigned int timer_grp2 : 1;
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unsigned int fifo_out1 : 1;
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unsigned int fifo_out1_extra : 1;
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unsigned int dmc_out1 : 1;
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unsigned int spu0_intr3 : 1;
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unsigned int spu1_intr3 : 1;
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unsigned int trigger_grp3 : 1;
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unsigned int trigger_grp7 : 1;
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unsigned int timer_grp3 : 1;
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unsigned int fifo_in1 : 1;
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unsigned int fifo_in1_extra : 1;
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unsigned int dmc_in1 : 1;
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} reg_iop_sw_mpu_rw_intr_grp0_mask;
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#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
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#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
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/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
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typedef struct {
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unsigned int spu0_intr0 : 1;
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unsigned int spu1_intr0 : 1;
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unsigned int dummy1 : 6;
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unsigned int spu0_intr1 : 1;
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unsigned int spu1_intr1 : 1;
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unsigned int dummy2 : 6;
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unsigned int spu0_intr2 : 1;
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unsigned int spu1_intr2 : 1;
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unsigned int dummy3 : 6;
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unsigned int spu0_intr3 : 1;
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unsigned int spu1_intr3 : 1;
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unsigned int dummy4 : 6;
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} reg_iop_sw_mpu_rw_ack_intr_grp0;
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#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
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#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
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/* Register r_intr_grp0, scope iop_sw_mpu, type r */
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typedef struct {
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unsigned int spu0_intr0 : 1;
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unsigned int spu1_intr0 : 1;
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unsigned int trigger_grp0 : 1;
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unsigned int trigger_grp4 : 1;
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unsigned int timer_grp0 : 1;
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unsigned int fifo_out0 : 1;
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unsigned int fifo_out0_extra : 1;
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unsigned int dmc_out0 : 1;
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unsigned int spu0_intr1 : 1;
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unsigned int spu1_intr1 : 1;
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unsigned int trigger_grp1 : 1;
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unsigned int trigger_grp5 : 1;
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unsigned int timer_grp1 : 1;
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unsigned int fifo_in0 : 1;
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unsigned int fifo_in0_extra : 1;
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unsigned int dmc_in0 : 1;
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unsigned int spu0_intr2 : 1;
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unsigned int spu1_intr2 : 1;
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unsigned int trigger_grp2 : 1;
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unsigned int trigger_grp6 : 1;
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unsigned int timer_grp2 : 1;
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unsigned int fifo_out1 : 1;
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unsigned int fifo_out1_extra : 1;
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unsigned int dmc_out1 : 1;
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unsigned int spu0_intr3 : 1;
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unsigned int spu1_intr3 : 1;
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unsigned int trigger_grp3 : 1;
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unsigned int trigger_grp7 : 1;
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unsigned int timer_grp3 : 1;
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unsigned int fifo_in1 : 1;
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unsigned int fifo_in1_extra : 1;
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unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_intr_grp0;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
|
|
|
|
/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr0 : 1;
|
|
unsigned int spu1_intr0 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr1 : 1;
|
|
unsigned int spu1_intr1 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr2 : 1;
|
|
unsigned int spu1_intr2 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr3 : 1;
|
|
unsigned int spu1_intr3 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_masked_intr_grp0;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
|
|
|
|
/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr4 : 1;
|
|
unsigned int spu1_intr4 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr5 : 1;
|
|
unsigned int spu1_intr5 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr6 : 1;
|
|
unsigned int spu1_intr6 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr7 : 1;
|
|
unsigned int spu1_intr7 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_rw_intr_grp1_mask;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
|
|
|
|
/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr4 : 1;
|
|
unsigned int spu1_intr4 : 1;
|
|
unsigned int dummy1 : 6;
|
|
unsigned int spu0_intr5 : 1;
|
|
unsigned int spu1_intr5 : 1;
|
|
unsigned int dummy2 : 6;
|
|
unsigned int spu0_intr6 : 1;
|
|
unsigned int spu1_intr6 : 1;
|
|
unsigned int dummy3 : 6;
|
|
unsigned int spu0_intr7 : 1;
|
|
unsigned int spu1_intr7 : 1;
|
|
unsigned int dummy4 : 6;
|
|
} reg_iop_sw_mpu_rw_ack_intr_grp1;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
|
|
|
|
/* Register r_intr_grp1, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr4 : 1;
|
|
unsigned int spu1_intr4 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr5 : 1;
|
|
unsigned int spu1_intr5 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr6 : 1;
|
|
unsigned int spu1_intr6 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr7 : 1;
|
|
unsigned int spu1_intr7 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_intr_grp1;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
|
|
|
|
/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr4 : 1;
|
|
unsigned int spu1_intr4 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr5 : 1;
|
|
unsigned int spu1_intr5 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr6 : 1;
|
|
unsigned int spu1_intr6 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr7 : 1;
|
|
unsigned int spu1_intr7 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_masked_intr_grp1;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
|
|
|
|
/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr8 : 1;
|
|
unsigned int spu1_intr8 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr9 : 1;
|
|
unsigned int spu1_intr9 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr10 : 1;
|
|
unsigned int spu1_intr10 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr11 : 1;
|
|
unsigned int spu1_intr11 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_rw_intr_grp2_mask;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
|
|
|
|
/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr8 : 1;
|
|
unsigned int spu1_intr8 : 1;
|
|
unsigned int dummy1 : 6;
|
|
unsigned int spu0_intr9 : 1;
|
|
unsigned int spu1_intr9 : 1;
|
|
unsigned int dummy2 : 6;
|
|
unsigned int spu0_intr10 : 1;
|
|
unsigned int spu1_intr10 : 1;
|
|
unsigned int dummy3 : 6;
|
|
unsigned int spu0_intr11 : 1;
|
|
unsigned int spu1_intr11 : 1;
|
|
unsigned int dummy4 : 6;
|
|
} reg_iop_sw_mpu_rw_ack_intr_grp2;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
|
|
|
|
/* Register r_intr_grp2, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr8 : 1;
|
|
unsigned int spu1_intr8 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr9 : 1;
|
|
unsigned int spu1_intr9 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr10 : 1;
|
|
unsigned int spu1_intr10 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr11 : 1;
|
|
unsigned int spu1_intr11 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_intr_grp2;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
|
|
|
|
/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr8 : 1;
|
|
unsigned int spu1_intr8 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr9 : 1;
|
|
unsigned int spu1_intr9 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr10 : 1;
|
|
unsigned int spu1_intr10 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr11 : 1;
|
|
unsigned int spu1_intr11 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_masked_intr_grp2;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
|
|
|
|
/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr12 : 1;
|
|
unsigned int spu1_intr12 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr13 : 1;
|
|
unsigned int spu1_intr13 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr14 : 1;
|
|
unsigned int spu1_intr14 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr15 : 1;
|
|
unsigned int spu1_intr15 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_rw_intr_grp3_mask;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
|
|
|
|
/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
|
|
typedef struct {
|
|
unsigned int spu0_intr12 : 1;
|
|
unsigned int spu1_intr12 : 1;
|
|
unsigned int dummy1 : 6;
|
|
unsigned int spu0_intr13 : 1;
|
|
unsigned int spu1_intr13 : 1;
|
|
unsigned int dummy2 : 6;
|
|
unsigned int spu0_intr14 : 1;
|
|
unsigned int spu1_intr14 : 1;
|
|
unsigned int dummy3 : 6;
|
|
unsigned int spu0_intr15 : 1;
|
|
unsigned int spu1_intr15 : 1;
|
|
unsigned int dummy4 : 6;
|
|
} reg_iop_sw_mpu_rw_ack_intr_grp3;
|
|
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
|
|
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
|
|
|
|
/* Register r_intr_grp3, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr12 : 1;
|
|
unsigned int spu1_intr12 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr13 : 1;
|
|
unsigned int spu1_intr13 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr14 : 1;
|
|
unsigned int spu1_intr14 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr15 : 1;
|
|
unsigned int spu1_intr15 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
|
|
} reg_iop_sw_mpu_r_intr_grp3;
|
|
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
|
|
|
|
/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
|
|
typedef struct {
|
|
unsigned int spu0_intr12 : 1;
|
|
unsigned int spu1_intr12 : 1;
|
|
unsigned int trigger_grp0 : 1;
|
|
unsigned int trigger_grp7 : 1;
|
|
unsigned int timer_grp0 : 1;
|
|
unsigned int fifo_in1 : 1;
|
|
unsigned int fifo_in1_extra : 1;
|
|
unsigned int dmc_out0 : 1;
|
|
unsigned int spu0_intr13 : 1;
|
|
unsigned int spu1_intr13 : 1;
|
|
unsigned int trigger_grp1 : 1;
|
|
unsigned int trigger_grp4 : 1;
|
|
unsigned int timer_grp1 : 1;
|
|
unsigned int fifo_out0 : 1;
|
|
unsigned int fifo_out0_extra : 1;
|
|
unsigned int dmc_in0 : 1;
|
|
unsigned int spu0_intr14 : 1;
|
|
unsigned int spu1_intr14 : 1;
|
|
unsigned int trigger_grp2 : 1;
|
|
unsigned int trigger_grp5 : 1;
|
|
unsigned int timer_grp2 : 1;
|
|
unsigned int fifo_in0 : 1;
|
|
unsigned int fifo_in0_extra : 1;
|
|
unsigned int dmc_out1 : 1;
|
|
unsigned int spu0_intr15 : 1;
|
|
unsigned int spu1_intr15 : 1;
|
|
unsigned int trigger_grp3 : 1;
|
|
unsigned int trigger_grp6 : 1;
|
|
unsigned int timer_grp3 : 1;
|
|
unsigned int fifo_out1 : 1;
|
|
unsigned int fifo_out1_extra : 1;
|
|
unsigned int dmc_in1 : 1;
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} reg_iop_sw_mpu_r_masked_intr_grp3;
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#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
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/* Constants */
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enum {
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regk_iop_sw_mpu_copy = 0x00000000,
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regk_iop_sw_mpu_cpu = 0x00000000,
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regk_iop_sw_mpu_mpu = 0x00000001,
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regk_iop_sw_mpu_no = 0x00000000,
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regk_iop_sw_mpu_nop = 0x00000000,
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regk_iop_sw_mpu_rd = 0x00000002,
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regk_iop_sw_mpu_reg_copy = 0x00000001,
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regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
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regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
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regk_iop_sw_mpu_set = 0x00000001,
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regk_iop_sw_mpu_spu0 = 0x00000002,
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regk_iop_sw_mpu_spu1 = 0x00000003,
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regk_iop_sw_mpu_wr = 0x00000003,
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regk_iop_sw_mpu_yes = 0x00000001
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};
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#endif /* __iop_sw_mpu_defs_h */
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