165 lines
7.2 KiB
C
165 lines
7.2 KiB
C
#ifndef __clkgen_defs_asm_h
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#define __clkgen_defs_asm_h
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/*
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* This file is autogenerated from
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* file: clkgen.r
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*
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* by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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#ifndef REG_FIELD
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#define REG_FIELD( scope, reg, field, value ) \
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REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_FIELD_X_( value, shift ) ((value) << shift)
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#endif
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#ifndef REG_STATE
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#define REG_STATE( scope, reg, field, symbolic_value ) \
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REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_STATE_X_( k, shift ) (k << shift)
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#endif
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#ifndef REG_MASK
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#define REG_MASK( scope, reg, field ) \
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REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
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#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
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#endif
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#ifndef REG_LSB
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#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
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#endif
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#ifndef REG_BIT
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#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
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#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
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STRIDE_##scope##_##reg )
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#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
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((inst) + offs + (index) * stride)
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#endif
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/* Register r_bootsel, scope clkgen, type r */
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#define reg_clkgen_r_bootsel___boot_mode___lsb 0
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#define reg_clkgen_r_bootsel___boot_mode___width 5
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#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
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#define reg_clkgen_r_bootsel___intern_main_clk___width 1
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#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
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#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
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#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
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#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
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#define reg_clkgen_r_bootsel_offset 0
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/* Register rw_clk_ctrl, scope clkgen, type rw */
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#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
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#define reg_clkgen_rw_clk_ctrl___pll___width 1
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#define reg_clkgen_rw_clk_ctrl___pll___bit 0
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#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
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#define reg_clkgen_rw_clk_ctrl___cpu___width 1
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#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
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#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
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#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
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#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
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#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
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#define reg_clkgen_rw_clk_ctrl___vin___width 1
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#define reg_clkgen_rw_clk_ctrl___vin___bit 3
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#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
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#define reg_clkgen_rw_clk_ctrl___sclr___width 1
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#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
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#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
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#define reg_clkgen_rw_clk_ctrl___h264___width 1
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#define reg_clkgen_rw_clk_ctrl___h264___bit 5
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#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
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#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
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#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
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#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
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#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
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#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
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#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
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#define reg_clkgen_rw_clk_ctrl___eth___width 1
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#define reg_clkgen_rw_clk_ctrl___eth___bit 8
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
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#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
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#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
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#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
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#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
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#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
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#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
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#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
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#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
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#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
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#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
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#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
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#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
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#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
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#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
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#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
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#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
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#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
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#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
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#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
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#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
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#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
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#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
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#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
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#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
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#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
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#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
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#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
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#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
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#define reg_clkgen_rw_clk_ctrl_offset 4
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/* Constants */
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#define regk_clkgen_eth1000_rx 0x0000000c
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#define regk_clkgen_eth1000_tx 0x0000000e
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#define regk_clkgen_eth100_rx 0x0000001d
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#define regk_clkgen_eth100_rx_half 0x0000001c
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#define regk_clkgen_eth100_tx 0x0000001f
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#define regk_clkgen_eth100_tx_half 0x0000001e
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#define regk_clkgen_nand_3_2 0x00000000
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#define regk_clkgen_nand_3_2_0x30 0x00000002
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#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
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#define regk_clkgen_nand_3_2_pll 0x00000010
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#define regk_clkgen_nand_3_3 0x00000001
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#define regk_clkgen_nand_3_3_0x30 0x00000003
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#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
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#define regk_clkgen_nand_3_3_pll 0x00000011
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#define regk_clkgen_nand_4_2 0x00000004
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#define regk_clkgen_nand_4_2_0x30 0x00000006
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#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
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#define regk_clkgen_nand_4_2_pll 0x00000014
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#define regk_clkgen_nand_4_3 0x00000005
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#define regk_clkgen_nand_4_3_0x30 0x00000007
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#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
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#define regk_clkgen_nand_4_3_pll 0x00000015
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#define regk_clkgen_nand_5_2 0x00000008
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#define regk_clkgen_nand_5_2_0x30 0x0000000a
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#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
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#define regk_clkgen_nand_5_2_pll 0x00000018
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#define regk_clkgen_nand_5_3 0x00000009
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#define regk_clkgen_nand_5_3_0x30 0x0000000b
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#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
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#define regk_clkgen_nand_5_3_pll 0x00000019
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#define regk_clkgen_no 0x00000000
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#define regk_clkgen_rw_clk_ctrl_default 0x00000002
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#define regk_clkgen_ser 0x0000000d
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#define regk_clkgen_ser_pll 0x0000000f
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#define regk_clkgen_yes 0x00000001
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#endif /* __clkgen_defs_asm_h */
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