6a0e243069
Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| abort-ev4.S | ||
| abort-ev4t.S | ||
| abort-ev5t.S | ||
| abort-ev5tj.S | ||
| abort-ev6.S | ||
| abort-lv4t.S | ||
| abort-macro.S | ||
| alignment.c | ||
| cache-v3.S | ||
| cache-v4.S | ||
| cache-v4wb.S | ||
| cache-v4wt.S | ||
| cache-v6.S | ||
| consistent.c | ||
| copypage-v3.S | ||
| copypage-v4mc.c | ||
| copypage-v4wb.S | ||
| copypage-v4wt.S | ||
| copypage-v6.c | ||
| copypage-xscale.c | ||
| discontig.c | ||
| extable.c | ||
| fault-armv.c | ||
| fault.c | ||
| fault.h | ||
| flush.c | ||
| init.c | ||
| ioremap.c | ||
| mm-armv.c | ||
| mmap.c | ||
| mmu.c | ||
| proc-arm6_7.S | ||
| proc-arm720.S | ||
| proc-arm920.S | ||
| proc-arm922.S | ||
| proc-arm925.S | ||
| proc-arm926.S | ||
| proc-arm1020.S | ||
| proc-arm1020e.S | ||
| proc-arm1022.S | ||
| proc-arm1026.S | ||
| proc-macros.S | ||
| proc-sa110.S | ||
| proc-sa1100.S | ||
| proc-syms.c | ||
| proc-v6.S | ||
| proc-xscale.S | ||
| tlb-v3.S | ||
| tlb-v4.S | ||
| tlb-v4wb.S | ||
| tlb-v4wbi.S | ||
| tlb-v6.S | ||