132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
#ifndef _IBM_EMAC_MAL_H
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#define _IBM_EMAC_MAL_H
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#include <linux/list.h>
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#define MAL_DT_ALIGN (4096) /* Alignment for each channel's descriptor table */
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#define MAL_CHAN_MASK(chan) (0x80000000 >> (chan))
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/* MAL Buffer Descriptor structure */
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struct mal_descriptor {
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unsigned short ctrl; /* MAL / Commac status control bits */
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short data_len; /* Max length is 4K-1 (12 bits) */
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unsigned char *data_ptr; /* pointer to actual data buffer */
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} __attribute__ ((packed));
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/* the following defines are for the MadMAL status and control registers. */
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/* MADMAL transmit and receive status/control bits */
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#define MAL_RX_CTRL_EMPTY 0x8000
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#define MAL_RX_CTRL_WRAP 0x4000
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#define MAL_RX_CTRL_CM 0x2000
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#define MAL_RX_CTRL_LAST 0x1000
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#define MAL_RX_CTRL_FIRST 0x0800
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#define MAL_RX_CTRL_INTR 0x0400
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#define MAL_TX_CTRL_READY 0x8000
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#define MAL_TX_CTRL_WRAP 0x4000
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#define MAL_TX_CTRL_CM 0x2000
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#define MAL_TX_CTRL_LAST 0x1000
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#define MAL_TX_CTRL_INTR 0x0400
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struct mal_commac_ops {
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void (*txeob) (void *dev, u32 chanmask);
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void (*txde) (void *dev, u32 chanmask);
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void (*rxeob) (void *dev, u32 chanmask);
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void (*rxde) (void *dev, u32 chanmask);
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};
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struct mal_commac {
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struct mal_commac_ops *ops;
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void *dev;
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u32 tx_chan_mask, rx_chan_mask;
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struct list_head list;
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};
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struct ibm_ocp_mal {
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int dcrbase;
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struct list_head commac;
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u32 tx_chan_mask, rx_chan_mask;
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dma_addr_t tx_phys_addr;
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struct mal_descriptor *tx_virt_addr;
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dma_addr_t rx_phys_addr;
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struct mal_descriptor *rx_virt_addr;
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};
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#define GET_MAL_STANZA(base,dcrn) \
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case base: \
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x = mfdcr(dcrn(base)); \
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break;
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#define SET_MAL_STANZA(base,dcrn, val) \
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case base: \
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mtdcr(dcrn(base), (val)); \
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break;
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#define GET_MAL0_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL_BASE,dcrn)
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#define SET_MAL0_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL_BASE,dcrn,val)
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#ifdef DCRN_MAL1_BASE
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#define GET_MAL1_STANZA(dcrn) GET_MAL_STANZA(DCRN_MAL1_BASE,dcrn)
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#define SET_MAL1_STANZA(dcrn,val) SET_MAL_STANZA(DCRN_MAL1_BASE,dcrn,val)
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#else /* ! DCRN_MAL1_BASE */
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#define GET_MAL1_STANZA(dcrn)
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#define SET_MAL1_STANZA(dcrn,val)
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#endif
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#define get_mal_dcrn(mal, dcrn) ({ \
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u32 x; \
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switch ((mal)->dcrbase) { \
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GET_MAL0_STANZA(dcrn) \
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GET_MAL1_STANZA(dcrn) \
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default: \
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x = 0; \
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BUG(); \
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} \
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x; })
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#define set_mal_dcrn(mal, dcrn, val) do { \
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switch ((mal)->dcrbase) { \
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SET_MAL0_STANZA(dcrn,val) \
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SET_MAL1_STANZA(dcrn,val) \
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default: \
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BUG(); \
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} } while (0)
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static inline void mal_enable_tx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
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{
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set_mal_dcrn(mal, DCRN_MALTXCASR,
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get_mal_dcrn(mal, DCRN_MALTXCASR) | chanmask);
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}
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static inline void mal_disable_tx_channels(struct ibm_ocp_mal *mal,
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u32 chanmask)
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{
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set_mal_dcrn(mal, DCRN_MALTXCARR, chanmask);
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}
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static inline void mal_enable_rx_channels(struct ibm_ocp_mal *mal, u32 chanmask)
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{
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set_mal_dcrn(mal, DCRN_MALRXCASR,
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get_mal_dcrn(mal, DCRN_MALRXCASR) | chanmask);
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}
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static inline void mal_disable_rx_channels(struct ibm_ocp_mal *mal,
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u32 chanmask)
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{
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set_mal_dcrn(mal, DCRN_MALRXCARR, chanmask);
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}
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extern int mal_register_commac(struct ibm_ocp_mal *mal,
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struct mal_commac *commac);
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extern int mal_unregister_commac(struct ibm_ocp_mal *mal,
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struct mal_commac *commac);
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extern int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel,
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unsigned long size);
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#endif /* _IBM_EMAC_MAL_H */
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