90303b1023
Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| ashldi3.S | ||
| ashrdi3.S | ||
| backtrace.S | ||
| bitops.h | ||
| changebit.S | ||
| clear_user.S | ||
| clearbit.S | ||
| copy_from_user.S | ||
| copy_page.S | ||
| copy_template.S | ||
| copy_to_user.S | ||
| csumipv6.S | ||
| csumpartial.S | ||
| csumpartialcopy.S | ||
| csumpartialcopygeneric.S | ||
| csumpartialcopyuser.S | ||
| delay.S | ||
| div64.S | ||
| ecard.S | ||
| findbit.S | ||
| floppydma.S | ||
| getuser.S | ||
| io-acorn.S | ||
| io-readsb.S | ||
| io-readsl.S | ||
| io-readsw-armv3.S | ||
| io-readsw-armv4.S | ||
| io-shark.c | ||
| io-writesb.S | ||
| io-writesl.S | ||
| io-writesw-armv3.S | ||
| io-writesw-armv4.S | ||
| lib1funcs.S | ||
| lshrdi3.S | ||
| memchr.S | ||
| memcpy.S | ||
| memmove.S | ||
| memset.S | ||
| memzero.S | ||
| muldi3.S | ||
| putuser.S | ||
| setbit.S | ||
| sha1.S | ||
| strchr.S | ||
| strncpy_from_user.S | ||
| strnlen_user.S | ||
| strrchr.S | ||
| testchangebit.S | ||
| testclearbit.S | ||
| testsetbit.S | ||
| uaccess.S | ||
| ucmpdi2.S | ||