188 lines
5.4 KiB
C
188 lines
5.4 KiB
C
/*
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* Low-Level PCI Support for the SH7751
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*
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* Copyright (C) 2003 - 2009 Paul Mundt
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* Copyright (C) 2001 Dustin McIntire
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*
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* With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include "pci-sh4.h"
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#include <asm/addrspace.h>
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static int __init __area_sdram_check(struct pci_channel *chan,
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unsigned int area)
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{
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unsigned long word;
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word = __raw_readl(SH7751_BCR1);
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/* check BCR for SDRAM in area */
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if (((word >> area) & 1) == 0) {
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printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
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area, word);
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return 0;
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}
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pci_write_reg(chan, word, SH4_PCIBCR1);
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word = __raw_readw(SH7751_BCR2);
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/* check BCR2 for 32bit SDRAM interface*/
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if (((word >> (area << 1)) & 0x3) != 0x3) {
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printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
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area, word);
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return 0;
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}
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pci_write_reg(chan, word, SH4_PCIBCR2);
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return 1;
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}
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static struct resource sh7751_io_resource = {
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.name = "SH7751_IO",
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.start = SH7751_PCI_IO_BASE,
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.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7751_mem_resource = {
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.name = "SH7751_mem",
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.start = SH7751_PCI_MEMORY_BASE,
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.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_channel sh7751_pci_controller = {
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.pci_ops = &sh4_pci_ops,
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.mem_resource = &sh7751_mem_resource,
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.mem_offset = 0x00000000,
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.io_resource = &sh7751_io_resource,
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.io_offset = 0x00000000,
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.io_map_base = SH7751_PCI_IO_BASE,
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};
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static struct sh4_pci_address_map sh7751_pci_map = {
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.window0 = {
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.base = SH7751_CS3_BASE_ADDR,
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.size = 0x04000000,
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},
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};
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static int __init sh7751_pci_init(void)
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{
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struct pci_channel *chan = &sh7751_pci_controller;
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unsigned int id;
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u32 word, reg;
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int ret;
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printk(KERN_NOTICE "PCI: Starting intialization.\n");
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chan->reg_base = 0xfe200000;
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/* check for SH7751/SH7751R hardware */
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id = pci_read_reg(chan, SH7751_PCICONF0);
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if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
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id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
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pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
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return -ENODEV;
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}
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if ((ret = sh4_pci_check_direct(chan)) != 0)
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return ret;
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/* Set the BCR's to enable PCI access */
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reg = ctrl_inl(SH7751_BCR1);
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reg |= 0x80000;
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ctrl_outl(reg, SH7751_BCR1);
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/* Turn the clocks back on (not done in reset)*/
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pci_write_reg(chan, 0, SH4_PCICLKR);
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/* Clear Powerdown IRQ's (not done in reset) */
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word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
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pci_write_reg(chan, word, SH4_PCIPINT);
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
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SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
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pci_write_reg(chan, word, SH7751_PCICONF1);
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/* define this host as the host bridge */
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word = PCI_BASE_CLASS_BRIDGE << 24;
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pci_write_reg(chan, word, SH7751_PCICONF2);
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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word = sh7751_pci_map.window0.size - 1;
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pci_write_reg(chan, word, SH4_PCILSR0);
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/* Set the values on window 0 PCI config registers */
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word = P2SEGADDR(sh7751_pci_map.window0.base);
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pci_write_reg(chan, word, SH4_PCILAR0);
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pci_write_reg(chan, word, SH7751_PCICONF5);
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/* Set the local 16MB PCI memory space window to
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* the lowest PCI mapped address
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*/
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word = chan->mem_resource->start & SH4_PCIMBR_MASK;
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pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
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pci_write_reg(chan, word , SH4_PCIMBR);
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/* Make sure the MSB's of IO window are set to access PCI space
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* correctly */
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word = chan->io_resource->start & SH4_PCIIOBR_MASK;
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pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
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pci_write_reg(chan, word, SH4_PCIIOBR);
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/* Set PCI WCRx, BCRx's, copy from BSC locations */
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/* check BCR for SDRAM in specified area */
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switch (sh7751_pci_map.window0.base) {
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case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
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case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
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case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
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case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
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case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
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case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
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case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
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}
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if (!word)
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return -1;
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/* configure the wait control registers */
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word = ctrl_inl(SH7751_WCR1);
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pci_write_reg(chan, word, SH4_PCIWCR1);
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word = ctrl_inl(SH7751_WCR2);
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pci_write_reg(chan, word, SH4_PCIWCR2);
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word = ctrl_inl(SH7751_WCR3);
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pci_write_reg(chan, word, SH4_PCIWCR3);
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word = ctrl_inl(SH7751_MCR);
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pci_write_reg(chan, word, SH4_PCIMCR);
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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* TODO: add support for the internal error interrupts and
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* DMA interrupts...
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*/
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pci_fixup_pcic(chan);
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/* SH7751 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
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pci_write_reg(chan, word, SH4_PCICR);
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register_pci_controller(chan);
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return 0;
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}
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arch_initcall(sh7751_pci_init);
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