295 lines
9.3 KiB
C
295 lines
9.3 KiB
C
/*
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* linux/arch/arm/mach-pxa/cpu-pxa.c
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*
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* Copyright (C) 2002,2003 Intrinsyc Software
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* History:
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* 31-Jul-2002 : Initial version [FB]
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* 29-Jan-2003 : added PXA255 support [FB]
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* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
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*
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* Note:
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* This driver may change the memory bus clock rate, but will not do any
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* platform specific access timing changes... for example if you have flash
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* memory connected to CS0, you will need to register a platform specific
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* notifier which will adjust the memory access strobes to maintain a
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* minimum strobe width.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-regs.h>
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#ifdef DEBUG
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static unsigned int freq_debug;
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MODULE_PARM(freq_debug, "i");
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MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
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#else
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#define freq_debug 0
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#endif
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typedef struct {
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unsigned int khz;
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unsigned int membus;
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unsigned int cccr;
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unsigned int div2;
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} pxa_freqs_t;
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
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#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define PXA25x_MIN_FREQ 99500
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#define PXA25x_MAX_FREQ 398100
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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static pxa_freqs_t pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2*/
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{ 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
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{132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
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{199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
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{265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
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{331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
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{398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
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{0,}
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};
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#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
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static pxa_freqs_t pxa255_turbo_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2*/
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{ 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
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{199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
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{298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
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{298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
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{398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
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{0,}
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};
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#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
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static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
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extern unsigned get_clk_frequency_khz(int info);
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/* find a valid frequency point */
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static int pxa_verify_policy(struct cpufreq_policy *policy)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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int ret;
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if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
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pxa_freqs_table = pxa255_run_freq_table;
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} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
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pxa_freqs_table = pxa255_turbo_freq_table;
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} else {
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printk("CPU PXA: Unknown policy found. "
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"Using CPUFREQ_POLICY_PERFORMANCE\n");
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pxa_freqs_table = pxa255_run_freq_table;
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}
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ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
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if (freq_debug)
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pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
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policy->min, policy->max);
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return ret;
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}
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static int pxa_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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pxa_freqs_t *pxa_freq_settings;
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struct cpufreq_freqs freqs;
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int idx;
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unsigned long flags;
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unsigned int unused, preset_mdrefr, postset_mdrefr;
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void *ramstart = phys_to_virt(0xa0000000);
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/* Get the current policy */
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if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
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pxa_freq_settings = pxa255_run_freqs;
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pxa_freqs_table = pxa255_run_freq_table;
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} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
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pxa_freq_settings = pxa255_turbo_freqs;
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pxa_freqs_table = pxa255_turbo_freq_table;
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} else {
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printk("CPU PXA: Unknown policy found. "
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"Using CPUFREQ_POLICY_PERFORMANCE\n");
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pxa_freq_settings = pxa255_run_freqs;
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pxa_freqs_table = pxa255_run_freq_table;
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}
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/* Lookup the next frequency */
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if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
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target_freq, relation, &idx)) {
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return -EINVAL;
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}
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freqs.old = policy->cur;
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freqs.new = pxa_freq_settings[idx].khz;
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freqs.cpu = policy->cpu;
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if (freq_debug)
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pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
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freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
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(pxa_freq_settings[idx].membus / 2000) :
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(pxa_freq_settings[idx].membus / 1000));
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/*
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* Tell everyone what we're about to do...
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* you should add a notify client with any platform specific
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* Vcc changing capability
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*/
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
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* we need to preset the smaller DRI before the change. If we're speeding
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* up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = MDREFR;
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if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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}
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postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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* after the change.
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*/
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if (pxa_freq_settings[idx].div2) {
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preset_mdrefr |= MDREFR_DB2_MASK;
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postset_mdrefr |= MDREFR_DB2_MASK;
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} else {
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postset_mdrefr &= ~MDREFR_DB2_MASK;
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}
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local_irq_save(flags);
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/* Set new the CCCR */
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CCCR = pxa_freq_settings[idx].cccr;
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asm volatile(" \n\
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ldr r4, [%1] /* load MDREFR */ \n\
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b 2f \n\
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.align 5 \n\
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1: \n\
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str %4, [%1] /* preset the MDREFR */ \n\
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mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
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str %5, [%1] /* postset the MDREFR */ \n\
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\n\
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b 3f \n\
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2: b 1b \n\
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3: nop \n\
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"
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: "=&r" (unused)
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: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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/*
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* Tell everyone what we've just done...
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* you should add a notify client with any platform specific
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* SDRAM refresh timer adjustments
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*/
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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{
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int i;
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/* set default policy and cpuinfo */
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->policy = CPUFREQ_POLICY_PERFORMANCE;
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policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
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policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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policy->cur = get_clk_frequency_khz(0); /* current freq */
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policy->min = policy->max = policy->cur;
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/* Generate the run cpufreq_frequency_table struct */
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for (i = 0; i < NUM_RUN_FREQS; i++) {
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pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
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pxa255_run_freq_table[i].index = i;
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}
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pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/* Generate the turbo cpufreq_frequency_table struct */
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for (i = 0; i < NUM_TURBO_FREQS; i++) {
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pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
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pxa255_turbo_freq_table[i].index = i;
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}
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pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
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printk(KERN_INFO "PXA CPU frequency change support initialized\n");
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return 0;
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}
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static struct cpufreq_driver pxa_cpufreq_driver = {
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.verify = pxa_verify_policy,
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.target = pxa_set_target,
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.init = pxa_cpufreq_init,
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.name = "PXA25x",
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};
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static int __init pxa_cpu_init(void)
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{
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int ret = -ENODEV;
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if (cpu_is_pxa25x())
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ret = cpufreq_register_driver(&pxa_cpufreq_driver);
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return ret;
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}
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static void __exit pxa_cpu_exit(void)
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{
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if (cpu_is_pxa25x())
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cpufreq_unregister_driver(&pxa_cpufreq_driver);
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}
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MODULE_AUTHOR ("Intrinsyc Software Inc.");
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MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
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MODULE_LICENSE("GPL");
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module_init(pxa_cpu_init);
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module_exit(pxa_cpu_exit);
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