250 lines
8.1 KiB
C
250 lines
8.1 KiB
C
/*
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* arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
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*
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* Initialize for ALi M1535+(included M5229 and M5237).
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for NEC-CMBVR4133 in 2.6
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* Author: Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <asm/vr41xx/cmbvr4133.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370)
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#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371)
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#define INDEX_PORT(port) CONFIG_PORT(port)
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#define ENTER_CONFIG_MODE(port) \
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do { \
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outb_p(0x51, CONFIG_PORT(port)); \
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outb_p(0x23, CONFIG_PORT(port)); \
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} while(0)
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#define SELECT_LOGICAL_DEVICE(port, dev_no) \
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do { \
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outb_p(0x07, INDEX_PORT(port)); \
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outb_p((dev_no), DATA_PORT(port)); \
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} while(0)
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#define WRITE_CONFIG_DATA(port, index, data) \
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do { \
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outb_p((index), INDEX_PORT(port)); \
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outb_p((data), DATA_PORT(port)); \
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} while(0)
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#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port))
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#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
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#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
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#ifdef CONFIG_BLK_DEV_FD
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void __devinit ali_m1535plus_fdc_init(int port)
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{
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ENTER_CONFIG_MODE(port);
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SELECT_LOGICAL_DEVICE(port, 0); /* FDC */
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WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */
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WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */
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WRITE_CONFIG_DATA(port, 0x61, 0xf0);
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WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */
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WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */
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WRITE_CONFIG_DATA(port, 0xf0, 0x08);
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WRITE_CONFIG_DATA(port, 0xf1, 0x00);
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WRITE_CONFIG_DATA(port, 0xf2, 0xff);
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WRITE_CONFIG_DATA(port, 0xf4, 0x00);
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EXIT_CONFIG_MODE(port);
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}
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#endif
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void __devinit ali_m1535plus_parport_init(int port)
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{
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ENTER_CONFIG_MODE(port);
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SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */
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WRITE_CONFIG_DATA(port, 0x30, 0x01);
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WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */
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WRITE_CONFIG_DATA(port, 0x61, 0x78);
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WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */
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WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */
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WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */
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WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
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EXIT_CONFIG_MODE(port);
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}
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void __devinit ali_m1535plus_keyboard_init(int port)
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{
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ENTER_CONFIG_MODE(port);
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SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */
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WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */
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WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */
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WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */
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WRITE_CONFIG_DATA(port, 0xf0, 0x00);
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EXIT_CONFIG_MODE(port);
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}
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void __devinit ali_m1535plus_hotkey_init(int port)
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{
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ENTER_CONFIG_MODE(port);
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SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */
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WRITE_CONFIG_DATA(port, 0x30, 0x00);
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WRITE_CONFIG_DATA(port, 0xf0, 0x35);
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WRITE_CONFIG_DATA(port, 0xf1, 0x14);
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WRITE_CONFIG_DATA(port, 0xf2, 0x11);
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WRITE_CONFIG_DATA(port, 0xf3, 0x71);
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WRITE_CONFIG_DATA(port, 0xf5, 0x05);
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EXIT_CONFIG_MODE(port);
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}
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void ali_m1535plus_init(struct pci_dev *dev)
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{
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pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
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pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
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pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
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pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
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pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
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pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
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pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
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/* IRQ routing */
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pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
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pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
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pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
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pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
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pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
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pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
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pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
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pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
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pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
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pci_write_config_byte(dev, 0x5a, 0x00);
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pci_write_config_byte(dev, 0x5b, 0x00);
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pci_write_config_word(dev, 0x5c, 0x0000);
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pci_write_config_byte(dev, 0x5e, 0x00);
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pci_write_config_byte(dev, 0x5f, 0x00);
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pci_write_config_word(dev, 0x60, 0x0000);
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pci_write_config_byte(dev, 0x6c, 0x00);
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pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
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pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
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pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
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pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
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pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
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pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
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/*
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* IRQ setup ALi M5237 USB Host Controller
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* IRQ: 9
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*/
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pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
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pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */
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pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
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pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
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pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
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pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
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pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
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pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
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pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
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#ifdef CONFIG_BLK_DEV_FD
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ali_m1535plus_fdc_init(1);
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#endif
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ali_m1535plus_keyboard_init(1);
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ali_m1535plus_hotkey_init(1);
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}
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static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
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{
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u32 data;
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int shift;
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writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
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data = readl(PCI_CONFIG_DATA);
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shift = (reg & 3) << 3;
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data &= ~(0xff << shift);
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data |= (((u32)val) << shift);
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writel(data, PCI_CONFIG_DATA);
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}
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static inline u8 ali_config_readb(u8 reg, int devfn)
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{
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u32 data;
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writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
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data = readl(PCI_CONFIG_DATA);
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return (u8)(data >> ((reg & 3) << 3));
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}
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static inline u16 ali_config_readw(u8 reg, int devfn)
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{
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u32 data;
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writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
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data = readl(PCI_CONFIG_DATA);
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return (u16)(data >> ((reg & 2) << 3));
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}
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int vr4133_rockhopper = 0;
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void __init ali_m5229_preinit(void)
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{
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if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
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ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
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printk(KERN_INFO "Found an NEC Rockhopper \n");
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vr4133_rockhopper = 1;
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/*
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* Enable ALi M5229 IDE Controller (both channels)
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* IDSEL: A27
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*/
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ali_config_writeb(0x58, 0x4c, 16);
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}
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}
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void __init ali_m5229_init(struct pci_dev *dev)
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{
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/*
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* Enable Primary/Secondary Channel Cable Detect 40-Pin
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*/
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pci_write_config_word(dev, 0x4a, 0xc023);
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/*
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* Set only the 3rd byteis for the master IDE's cycle and
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* enable Internal IDE Function
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*/
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pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
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pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
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pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
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pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
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pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
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pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
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pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
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pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
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pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
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pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
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pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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pci_write_config_word(dev, PCI_COMMAND,
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PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
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PCI_COMMAND_IO);
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}
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