516 lines
14 KiB
C
516 lines
14 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Au1000 Power Management routines.
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Some of the routines are right out of init/main.c, whose
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* copyrights apply here.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/pm_legacy.h>
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#include <linux/slab.h>
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#include <linux/sysctl.h>
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#include <linux/jiffies.h>
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#include <asm/string.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_PM
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#define DEBUG 1
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#ifdef DEBUG
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# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
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#else
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# define DPRINTK(fmt, args...)
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#endif
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static void au1000_calibrate_delay(void);
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extern void set_au1x00_speed(unsigned int new_freq);
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extern unsigned int get_au1x00_speed(void);
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extern unsigned long get_au1x00_uart_baud_base(void);
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extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
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extern unsigned long save_local_and_disable(int controller);
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extern void restore_local_and_enable(int controller, unsigned long mask);
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extern void local_enable_irq(unsigned int irq_nr);
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static DEFINE_SPINLOCK(pm_lock);
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/* We need to save/restore a bunch of core registers that are
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* either volatile or reset to some state across a processor sleep.
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* If reading a register doesn't provide a proper result for a
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* later restore, we have to provide a function for loading that
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* register and save a copy.
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*
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* We only have to save/restore registers that aren't otherwise
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* done as part of a driver pm_* function.
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*/
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static unsigned int sleep_aux_pll_cntrl;
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static unsigned int sleep_cpu_pll_cntrl;
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static unsigned int sleep_pin_function;
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static unsigned int sleep_uart0_inten;
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static unsigned int sleep_uart0_fifoctl;
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static unsigned int sleep_uart0_linectl;
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static unsigned int sleep_uart0_clkdiv;
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static unsigned int sleep_uart0_enable;
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static unsigned int sleep_usbhost_enable;
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static unsigned int sleep_usbdev_enable;
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static unsigned int sleep_static_memctlr[4][3];
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/* Define this to cause the value you write to /proc/sys/pm/sleep to
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* set the TOY timer for the amount of time you want to sleep.
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* This is done mainly for testing, but may be useful in other cases.
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* The value is number of 32KHz ticks to sleep.
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*/
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#define SLEEP_TEST_TIMEOUT 1
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#ifdef SLEEP_TEST_TIMEOUT
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static int sleep_ticks;
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void wakeup_counter0_set(int ticks);
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#endif
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static void
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save_core_regs(void)
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{
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extern void save_au1xxx_intctl(void);
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extern void pm_eth0_shutdown(void);
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/* Do the serial ports.....these really should be a pm_*
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* registered function by the driver......but of course the
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* standard serial driver doesn't understand our Au1xxx
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* unique registers.
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*/
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sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
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sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
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sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
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sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
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sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
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/* Shutdown USB host/device.
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*/
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sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
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/* There appears to be some undocumented reset register....
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*/
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au_writel(0, 0xb0100004); au_sync();
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au_writel(0, USB_HOST_CONFIG); au_sync();
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sleep_usbdev_enable = au_readl(USBD_ENABLE);
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au_writel(0, USBD_ENABLE); au_sync();
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/* Save interrupt controller state.
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*/
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save_au1xxx_intctl();
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/* Clocks and PLLs.
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*/
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sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
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/* We don't really need to do this one, but unless we
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* write it again it won't have a valid value if we
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* happen to read it.
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*/
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sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
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sleep_pin_function = au_readl(SYS_PINFUNC);
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/* Save the static memory controller configuration.
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*/
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sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
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sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
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sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
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sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
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sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
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sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
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sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
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sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
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sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
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sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
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sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
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sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
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}
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static void
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restore_core_regs(void)
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{
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extern void restore_au1xxx_intctl(void);
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extern void wakeup_counter0_adjust(void);
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au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync();
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au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
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au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
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/* Restore the static memory controller configuration.
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*/
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au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
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au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
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au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
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au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
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au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
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au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
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au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
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au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
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au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
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au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
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au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
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au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
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/* Enable the UART if it was enabled before sleep.
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* I guess I should define module control bits........
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*/
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if (sleep_uart0_enable & 0x02) {
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au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
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au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
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au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
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au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
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}
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restore_au1xxx_intctl();
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wakeup_counter0_adjust();
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}
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unsigned long suspend_mode;
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void wakeup_from_suspend(void)
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{
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suspend_mode = 0;
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}
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int au_sleep(void)
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{
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unsigned long wakeup, flags;
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extern void save_and_sleep(void);
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spin_lock_irqsave(&pm_lock, flags);
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save_core_regs();
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flush_cache_all();
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/** The code below is all system dependent and we should probably
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** have a function call out of here to set this up. You need
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** to configure the GPIO or timer interrupts that will bring
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** you out of sleep.
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** For testing, the TOY counter wakeup is useful.
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**/
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#if 0
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au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
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/* gpio 6 can cause a wake up event */
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wakeup = au_readl(SYS_WAKEMSK);
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wakeup &= ~(1 << 8); /* turn off match20 wakeup */
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wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
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#else
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/* For testing, allow match20 to wake us up.
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*/
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#ifdef SLEEP_TEST_TIMEOUT
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wakeup_counter0_set(sleep_ticks);
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#endif
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wakeup = 1 << 8; /* turn on match20 wakeup */
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wakeup = 0;
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#endif
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au_writel(1, SYS_WAKESRC); /* clear cause */
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au_sync();
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au_writel(wakeup, SYS_WAKEMSK);
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au_sync();
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save_and_sleep();
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/* after a wakeup, the cpu vectors back to 0x1fc00000 so
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* it's up to the boot code to get us back here.
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*/
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restore_core_regs();
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spin_unlock_irqrestore(&pm_lock, flags);
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return 0;
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}
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static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
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void __user *buffer, size_t * len, loff_t *ppos)
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{
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int retval = 0;
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#ifdef SLEEP_TEST_TIMEOUT
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#define TMPBUFLEN2 16
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char buf[TMPBUFLEN2], *p;
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#endif
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if (!write) {
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*len = 0;
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} else {
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#ifdef SLEEP_TEST_TIMEOUT
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if (*len > TMPBUFLEN2 - 1) {
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return -EFAULT;
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}
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if (copy_from_user(buf, buffer, *len)) {
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return -EFAULT;
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}
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buf[*len] = 0;
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p = buf;
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sleep_ticks = simple_strtoul(p, &p, 0);
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#endif
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retval = pm_send_all(PM_SUSPEND, (void *) 2);
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if (retval)
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return retval;
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au_sleep();
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retval = pm_send_all(PM_RESUME, (void *) 0);
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}
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return retval;
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}
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static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
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void __user *buffer, size_t * len, loff_t *ppos)
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{
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int retval = 0;
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if (!write) {
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*len = 0;
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} else {
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retval = pm_send_all(PM_SUSPEND, (void *) 2);
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if (retval)
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return retval;
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suspend_mode = 1;
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retval = pm_send_all(PM_RESUME, (void *) 0);
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}
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return retval;
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}
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static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
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void __user *buffer, size_t * len, loff_t *ppos)
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{
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int retval = 0, i;
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unsigned long val, pll;
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#define TMPBUFLEN 64
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#define MAX_CPU_FREQ 396
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char buf[TMPBUFLEN], *p;
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unsigned long flags, intc0_mask, intc1_mask;
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unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
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old_refresh;
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unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
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spin_lock_irqsave(&pm_lock, flags);
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if (!write) {
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*len = 0;
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} else {
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/* Parse the new frequency */
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if (*len > TMPBUFLEN - 1) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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if (copy_from_user(buf, buffer, *len)) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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buf[*len] = 0;
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p = buf;
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val = simple_strtoul(p, &p, 0);
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if (val > MAX_CPU_FREQ) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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pll = val / 12;
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if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
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/* revisit this for higher speed cpus */
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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old_baud_base = get_au1x00_uart_baud_base();
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old_cpu_freq = get_au1x00_speed();
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new_cpu_freq = pll * 12 * 1000000;
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new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
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set_au1x00_speed(new_cpu_freq);
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set_au1x00_uart_baud_base(new_baud_base);
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old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
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new_refresh =
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((old_refresh * new_cpu_freq) /
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old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
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au_writel(pll, SYS_CPUPLL);
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au_sync_delay(1);
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au_writel(new_refresh, MEM_SDREFCFG);
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au_sync_delay(1);
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for (i = 0; i < 4; i++) {
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if (au_readl
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(UART_BASE + UART_MOD_CNTRL +
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i * 0x00100000) == 3) {
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old_clk =
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au_readl(UART_BASE + UART_CLK +
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i * 0x00100000);
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// baud_rate = baud_base/clk
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baud_rate = old_baud_base / old_clk;
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/* we won't get an exact baud rate and the error
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* could be significant enough that our new
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* calculation will result in a clock that will
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* give us a baud rate that's too far off from
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* what we really want.
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*/
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if (baud_rate > 100000)
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baud_rate = 115200;
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else if (baud_rate > 50000)
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baud_rate = 57600;
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else if (baud_rate > 30000)
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baud_rate = 38400;
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else if (baud_rate > 17000)
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baud_rate = 19200;
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else
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(baud_rate = 9600);
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// new_clk = new_baud_base/baud_rate
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new_clk = new_baud_base / baud_rate;
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au_writel(new_clk,
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UART_BASE + UART_CLK +
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i * 0x00100000);
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au_sync_delay(10);
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}
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}
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}
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/*
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* We don't want _any_ interrupts other than match20. Otherwise our
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* au1000_calibrate_delay() calculation will be off, potentially a lot.
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*/
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intc0_mask = save_local_and_disable(0);
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intc1_mask = save_local_and_disable(1);
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local_enable_irq(AU1000_TOY_MATCH2_INT);
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spin_unlock_irqrestore(&pm_lock, flags);
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au1000_calibrate_delay();
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restore_local_and_enable(0, intc0_mask);
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restore_local_and_enable(1, intc1_mask);
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return retval;
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}
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static struct ctl_table pm_table[] = {
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "suspend",
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.data = NULL,
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.maxlen = 0,
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.mode = 0600,
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.proc_handler = &pm_do_suspend
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},
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "sleep",
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.data = NULL,
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.maxlen = 0,
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.mode = 0600,
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.proc_handler = &pm_do_sleep
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},
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "freq",
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.data = NULL,
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.maxlen = 0,
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.mode = 0600,
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.proc_handler = &pm_do_freq
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},
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{}
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};
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static struct ctl_table pm_dir_table[] = {
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "pm",
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.mode = 0555,
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.child = pm_table
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},
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{}
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};
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/*
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* Initialize power interface
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*/
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static int __init pm_init(void)
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{
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register_sysctl_table(pm_dir_table);
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return 0;
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}
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__initcall(pm_init);
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/*
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* This is right out of init/main.c
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*/
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/* This is the number of bits of precision for the loops_per_jiffy. Each
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bit takes on average 1.5/HZ seconds. This (like the original) is a little
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better than 1% */
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#define LPS_PREC 8
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static void au1000_calibrate_delay(void)
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{
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unsigned long ticks, loopbit;
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int lps_precision = LPS_PREC;
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loops_per_jiffy = (1 << 12);
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while (loops_per_jiffy <<= 1) {
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/* wait for "start of" clock tick */
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ticks = jiffies;
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while (ticks == jiffies)
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/* nothing */ ;
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/* Go .. */
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ticks = jiffies;
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__delay(loops_per_jiffy);
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ticks = jiffies - ticks;
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if (ticks)
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break;
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}
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/* Do a binary approximation to get loops_per_jiffy set to equal one clock
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(up to lps_precision bits) */
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loops_per_jiffy >>= 1;
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loopbit = loops_per_jiffy;
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while (lps_precision-- && (loopbit >>= 1)) {
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loops_per_jiffy |= loopbit;
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ticks = jiffies;
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while (ticks == jiffies);
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ticks = jiffies;
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__delay(loops_per_jiffy);
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if (jiffies != ticks) /* longer than 1 tick */
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loops_per_jiffy &= ~loopbit;
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}
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}
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#endif /* CONFIG_PM */
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