323 lines
7.8 KiB
C
323 lines
7.8 KiB
C
/*
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* olympic.h (c) 1999 Peter De Schrijver All Rights Reserved
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* 1999,2000 Mike Phillips (mikep@linuxtr.net)
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*
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* Linux driver for IBM PCI tokenring cards based on the olympic and the PIT/PHY chipset.
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*
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* Base Driver Skeleton:
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* Written 1993-94 by Donald Becker.
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*
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* Copyright 1993 United States Government as represented by the
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* Director, National Security Agency.
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*/
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#define CID 0x4e
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#define BCTL 0x70
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#define BCTL_SOFTRESET (1<<15)
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#define BCTL_MIMREB (1<<6)
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#define BCTL_MODE_INDICATOR (1<<5)
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#define GPR 0x4a
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#define GPR_OPTI_BF (1<<6)
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#define GPR_NEPTUNE_BF (1<<4)
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#define GPR_AUTOSENSE (1<<2)
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#define GPR_16MBPS (1<<3)
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#define PAG 0x85
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#define LBC 0x8e
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#define LISR 0x10
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#define LISR_SUM 0x14
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#define LISR_RWM 0x18
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#define LISR_LIE (1<<15)
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#define LISR_SLIM (1<<13)
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#define LISR_SLI (1<<12)
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#define LISR_PCMSRMASK (1<<11)
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#define LISR_PCMSRINT (1<<10)
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#define LISR_WOLMASK (1<<9)
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#define LISR_WOL (1<<8)
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#define LISR_SRB_CMD (1<<5)
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#define LISR_ASB_REPLY (1<<4)
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#define LISR_ASB_FREE_REQ (1<<2)
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#define LISR_ARB_FREE (1<<1)
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#define LISR_TRB_FRAME (1<<0)
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#define SISR 0x20
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#define SISR_SUM 0x24
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#define SISR_RWM 0x28
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#define SISR_RR 0x2C
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#define SISR_RESMASK 0x30
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#define SISR_MASK 0x54
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#define SISR_MASK_SUM 0x58
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#define SISR_MASK_RWM 0x5C
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#define SISR_TX2_IDLE (1<<31)
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#define SISR_TX2_HALT (1<<29)
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#define SISR_TX2_EOF (1<<28)
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#define SISR_TX1_IDLE (1<<27)
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#define SISR_TX1_HALT (1<<25)
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#define SISR_TX1_EOF (1<<24)
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#define SISR_TIMEOUT (1<<23)
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#define SISR_RX_NOBUF (1<<22)
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#define SISR_RX_STATUS (1<<21)
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#define SISR_RX_HALT (1<<18)
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#define SISR_RX_EOF_EARLY (1<<16)
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#define SISR_MI (1<<15)
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#define SISR_PI (1<<13)
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#define SISR_ERR (1<<9)
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#define SISR_ADAPTER_CHECK (1<<6)
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#define SISR_SRB_REPLY (1<<5)
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#define SISR_ASB_FREE (1<<4)
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#define SISR_ARB_CMD (1<<3)
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#define SISR_TRB_REPLY (1<<2)
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#define EISR 0x34
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#define EISR_RWM 0x38
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#define EISR_MASK 0x3c
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#define EISR_MASK_OPTIONS 0x001FFF7F
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#define LAPA 0x60
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#define LAPWWO 0x64
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#define LAPWWC 0x68
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#define LAPCTL 0x6C
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#define LAIPD 0x78
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#define LAIPDDINC 0x7C
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#define TIMER 0x50
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#define CLKCTL 0x74
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#define CLKCTL_PAUSE (1<<15)
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#define PM_CON 0x4
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#define BMCTL_SUM 0x40
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#define BMCTL_RWM 0x44
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#define BMCTL_TX2_DIS (1<<30)
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#define BMCTL_TX1_DIS (1<<26)
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#define BMCTL_RX_DIS (1<<22)
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#define BMASR 0xcc
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#define RXDESCQ 0x90
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#define RXDESCQCNT 0x94
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#define RXCDA 0x98
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#define RXENQ 0x9C
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#define RXSTATQ 0xA0
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#define RXSTATQCNT 0xA4
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#define RXCSA 0xA8
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#define RXCLEN 0xAC
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#define RXHLEN 0xAE
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#define TXDESCQ_1 0xb0
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#define TXDESCQ_2 0xd0
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#define TXDESCQCNT_1 0xb4
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#define TXDESCQCNT_2 0xd4
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#define TXCDA_1 0xb8
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#define TXCDA_2 0xd8
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#define TXENQ_1 0xbc
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#define TXENQ_2 0xdc
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#define TXSTATQ_1 0xc0
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#define TXSTATQ_2 0xe0
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#define TXSTATQCNT_1 0xc4
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#define TXSTATQCNT_2 0xe4
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#define TXCSA_1 0xc8
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#define TXCSA_2 0xe8
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/* Cardbus */
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#define FERMASK 0xf4
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#define FERMASK_INT_BIT (1<<15)
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#define OLYMPIC_IO_SPACE 256
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#define SRB_COMMAND_SIZE 50
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#define OLYMPIC_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
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/* Defines for LAN STATUS CHANGE reports */
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#define LSC_SIG_LOSS 0x8000
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#define LSC_HARD_ERR 0x4000
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#define LSC_SOFT_ERR 0x2000
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#define LSC_TRAN_BCN 0x1000
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#define LSC_LWF 0x0800
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#define LSC_ARW 0x0400
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#define LSC_FPE 0x0200
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#define LSC_RR 0x0100
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#define LSC_CO 0x0080
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#define LSC_SS 0x0040
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#define LSC_RING_REC 0x0020
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#define LSC_SR_CO 0x0010
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#define LSC_FDX_MODE 0x0004
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/* Defines for OPEN ADAPTER command */
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#define OPEN_ADAPTER_EXT_WRAP (1<<15)
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#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
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#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
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#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
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#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
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#define OPEN_ADAPTER_ENABLE_EC (1<<10)
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#define OPEN_ADAPTER_CONTENDER (1<<8)
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#define OPEN_ADAPTER_PASS_BEACON (1<<7)
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#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
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#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
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#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
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#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
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#define OPEN_ADAPTER_USE_OPTS2 (1<<0)
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#define OPEN_ADAPTER_2_ENABLE_ONNOW (1<<15)
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/* Defines for SRB Commands */
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#define SRB_ACCESS_REGISTER 0x1f
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#define SRB_CLOSE_ADAPTER 0x04
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#define SRB_CONFIGURE_BRIDGE 0x0c
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#define SRB_CONFIGURE_WAKEUP_EVENT 0x1a
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#define SRB_MODIFY_BRIDGE_PARMS 0x15
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#define SRB_MODIFY_OPEN_OPTIONS 0x01
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#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
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#define SRB_NO_OPERATION 0x00
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#define SRB_OPEN_ADAPTER 0x03
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#define SRB_READ_LOG 0x08
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#define SRB_READ_SR_COUNTERS 0x16
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#define SRB_RESET_GROUP_ADDRESS 0x02
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#define SRB_SAVE_CONFIGURATION 0x1b
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#define SRB_SET_BRIDGE_PARMS 0x09
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#define SRB_SET_BRIDGE_TARGETS 0x10
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#define SRB_SET_FUNC_ADDRESS 0x07
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#define SRB_SET_GROUP_ADDRESS 0x06
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#define SRB_SET_GROUP_ADDR_OPTIONS 0x11
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#define SRB_UPDATE_WAKEUP_PATTERN 0x19
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/* Clear return code */
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#define OLYMPIC_CLEAR_RET_CODE 0xfe
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/* ARB Commands */
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#define ARB_RECEIVE_DATA 0x81
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#define ARB_LAN_CHANGE_STATUS 0x84
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/* ASB Response commands */
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#define ASB_RECEIVE_DATA 0x81
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/* Olympic defaults for buffers */
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#define OLYMPIC_RX_RING_SIZE 16 /* should be a power of 2 */
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#define OLYMPIC_TX_RING_SIZE 8 /* should be a power of 2 */
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#define PKT_BUF_SZ 4096 /* Default packet size */
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/* Olympic data structures */
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/* xxxx These structures are all little endian in hardware. */
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struct olympic_tx_desc {
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__le32 buffer;
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__le32 status_length;
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};
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struct olympic_tx_status {
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__le32 status;
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};
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struct olympic_rx_desc {
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__le32 buffer;
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__le32 res_length;
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};
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struct olympic_rx_status {
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__le32 fragmentcnt_framelen;
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__le32 status_buffercnt;
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};
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/* xxxx END These structures are all little endian in hardware. */
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/* xxxx There may be more, but I'm pretty sure about these */
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struct mac_receive_buffer {
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__le16 next ;
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u8 padding ;
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u8 frame_status ;
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__le16 buffer_length ;
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u8 frame_data ;
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};
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struct olympic_private {
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u16 srb; /* be16 */
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u16 trb; /* be16 */
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u16 arb; /* be16 */
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u16 asb; /* be16 */
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u8 __iomem *olympic_mmio;
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u8 __iomem *olympic_lap;
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struct pci_dev *pdev ;
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const char *olympic_card_name;
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spinlock_t olympic_lock ;
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volatile int srb_queued; /* True if an SRB is still posted */
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wait_queue_head_t srb_wait;
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volatile int asb_queued; /* True if an ASB is posted */
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volatile int trb_queued; /* True if a TRB is posted */
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wait_queue_head_t trb_wait ;
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/* These must be on a 4 byte boundary. */
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struct olympic_rx_desc olympic_rx_ring[OLYMPIC_RX_RING_SIZE];
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struct olympic_tx_desc olympic_tx_ring[OLYMPIC_TX_RING_SIZE];
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struct olympic_rx_status olympic_rx_status_ring[OLYMPIC_RX_RING_SIZE];
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struct olympic_tx_status olympic_tx_status_ring[OLYMPIC_TX_RING_SIZE];
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struct sk_buff *tx_ring_skb[OLYMPIC_TX_RING_SIZE], *rx_ring_skb[OLYMPIC_RX_RING_SIZE];
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int tx_ring_free, tx_ring_last_status, rx_ring_last_received,rx_status_last_received, free_tx_ring_entries;
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struct net_device_stats olympic_stats ;
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u16 olympic_lan_status ;
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u8 olympic_ring_speed ;
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u16 pkt_buf_sz ;
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u8 olympic_receive_options, olympic_copy_all_options,olympic_message_level, olympic_network_monitor;
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u16 olympic_addr_table_addr, olympic_parms_addr ;
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u8 olympic_laa[6] ;
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u32 rx_ring_dma_addr;
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u32 rx_status_ring_dma_addr;
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u32 tx_ring_dma_addr;
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u32 tx_status_ring_dma_addr;
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};
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struct olympic_adapter_addr_table {
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u8 node_addr[6] ;
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u8 reserved[4] ;
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u8 func_addr[4] ;
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} ;
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struct olympic_parameters_table {
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u8 phys_addr[4] ;
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u8 up_node_addr[6] ;
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u8 up_phys_addr[4] ;
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u8 poll_addr[6] ;
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u16 reserved ;
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u16 acc_priority ;
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u16 auth_source_class ;
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u16 att_code ;
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u8 source_addr[6] ;
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u16 beacon_type ;
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u16 major_vector ;
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u16 lan_status ;
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u16 soft_error_time ;
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u16 reserved1 ;
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u16 local_ring ;
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u16 mon_error ;
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u16 beacon_transmit ;
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u16 beacon_receive ;
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u16 frame_correl ;
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u8 beacon_naun[6] ;
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u32 reserved2 ;
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u8 beacon_phys[4] ;
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};
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