211 lines
6.9 KiB
C
211 lines
6.9 KiB
C
/* savage_drm.h -- Public header for the savage driver
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*
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* Copyright 2004 Felix Kuehling
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __SAVAGE_DRM_H__
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#define __SAVAGE_DRM_H__
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#ifndef __SAVAGE_SAREA_DEFINES__
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#define __SAVAGE_SAREA_DEFINES__
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/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
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* regions, subject to a minimum region size of (1<<16) == 64k.
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*
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* Clients may subdivide regions internally, but when sharing between
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* clients, the region size is the minimum granularity.
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*/
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#define SAVAGE_CARD_HEAP 0
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#define SAVAGE_AGP_HEAP 1
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#define SAVAGE_NR_TEX_HEAPS 2
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#define SAVAGE_NR_TEX_REGIONS 16
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#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
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#endif /* __SAVAGE_SAREA_DEFINES__ */
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typedef struct _drm_savage_sarea {
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/* LRU lists for texture memory in agp space and on the card.
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*/
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struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
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1];
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unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
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/* Mechanism to validate card state.
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*/
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int ctxOwner;
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} drm_savage_sarea_t, *drm_savage_sarea_ptr;
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/* Savage-specific ioctls
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*/
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#define DRM_SAVAGE_BCI_INIT 0x00
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#define DRM_SAVAGE_BCI_CMDBUF 0x01
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#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
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#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
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#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
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#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
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#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
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#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
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#define SAVAGE_DMA_PCI 1
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#define SAVAGE_DMA_AGP 3
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typedef struct drm_savage_init {
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enum {
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SAVAGE_INIT_BCI = 1,
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SAVAGE_CLEANUP_BCI = 2
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} func;
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unsigned int sarea_priv_offset;
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/* some parameters */
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unsigned int cob_size;
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unsigned int bci_threshold_lo, bci_threshold_hi;
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unsigned int dma_type;
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/* frame buffer layout */
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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/* local textures */
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unsigned int texture_offset;
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unsigned int texture_size;
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/* physical locations of non-permanent maps */
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unsigned long status_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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unsigned long cmd_dma_offset;
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} drm_savage_init_t;
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typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
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typedef struct drm_savage_cmdbuf {
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/* command buffer in client's address space */
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drm_savage_cmd_header_t __user *cmd_addr;
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unsigned int size; /* size of the command buffer in 64bit units */
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unsigned int dma_idx; /* DMA buffer index to use */
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int discard; /* discard DMA buffer when done */
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/* vertex buffer in client's address space */
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unsigned int __user *vb_addr;
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unsigned int vb_size; /* size of client vertex buffer in bytes */
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unsigned int vb_stride; /* stride of vertices in 32bit words */
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/* boxes in client's address space */
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struct drm_clip_rect __user *box_addr;
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unsigned int nbox; /* number of clipping boxes */
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} drm_savage_cmdbuf_t;
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#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
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#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
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#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
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typedef struct drm_savage_event {
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unsigned int count;
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unsigned int flags;
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} drm_savage_event_emit_t, drm_savage_event_wait_t;
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/* Commands for the cmdbuf ioctl
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*/
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#define SAVAGE_CMD_STATE 0 /* a range of state registers */
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#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
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#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
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#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
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#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
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#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
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#define SAVAGE_CMD_SWAP 6 /* swap buffers */
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/* Primitive types
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*/
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#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
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#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
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#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
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#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
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* shading on s3d */
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/* Skip flags (vertex format)
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*/
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#define SAVAGE_SKIP_Z 0x01
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#define SAVAGE_SKIP_W 0x02
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#define SAVAGE_SKIP_C0 0x04
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#define SAVAGE_SKIP_C1 0x08
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#define SAVAGE_SKIP_S0 0x10
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#define SAVAGE_SKIP_T0 0x20
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#define SAVAGE_SKIP_ST0 0x30
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#define SAVAGE_SKIP_S1 0x40
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#define SAVAGE_SKIP_T1 0x80
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#define SAVAGE_SKIP_ST1 0xc0
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#define SAVAGE_SKIP_ALL_S3D 0x3f
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#define SAVAGE_SKIP_ALL_S4 0xff
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/* Buffer names for clear command
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*/
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#define SAVAGE_FRONT 0x1
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#define SAVAGE_BACK 0x2
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#define SAVAGE_DEPTH 0x4
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/* 64-bit command header
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*/
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union drm_savage_cmd_header {
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struct {
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unsigned char cmd; /* command */
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unsigned char pad0;
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unsigned short pad1;
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unsigned short pad2;
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unsigned short pad3;
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} cmd; /* generic */
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struct {
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unsigned char cmd;
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unsigned char global; /* need idle engine? */
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unsigned short count; /* number of consecutive registers */
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unsigned short start; /* first register */
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unsigned short pad3;
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} state; /* SAVAGE_CMD_STATE */
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struct {
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unsigned char cmd;
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unsigned char prim; /* primitive type */
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unsigned short skip; /* vertex format (skip flags) */
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unsigned short count; /* number of vertices */
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unsigned short start; /* first vertex in DMA/vertex buffer */
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} prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
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struct {
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unsigned char cmd;
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unsigned char prim;
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unsigned short skip;
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unsigned short count; /* number of indices that follow */
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unsigned short pad3;
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} idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
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struct {
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unsigned char cmd;
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unsigned char pad0;
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unsigned short pad1;
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unsigned int flags;
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} clear0; /* SAVAGE_CMD_CLEAR */
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struct {
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unsigned int mask;
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unsigned int value;
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} clear1; /* SAVAGE_CMD_CLEAR data */
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};
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#endif
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