136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
#ifndef _AD1889_H_
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#define _AD1889_H_
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#define AD_DS_WSMC 0x00 /* DMA input wave/syn mixer control */
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#define AD_DS_RAMC 0x02 /* DMA output resamp/ADC mixer control */
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#define AD_DS_WADA 0x04 /* DMA input wave attenuation */
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#define AD_DS_SYDA 0x06 /* DMA input syn attentuation */
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#define AD_DS_WAS 0x08 /* wave input sample rate */
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#define AD_DS_RES 0x0a /* resampler output sample rate */
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#define AD_DS_CCS 0x0c /* chip control/status */
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#define AD_DMA_RESBA 0x40 /* RES base addr */
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#define AD_DMA_RESCA 0x44 /* RES current addr */
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#define AD_DMA_RESBC 0x48 /* RES base cnt */
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#define AD_DMA_RESCC 0x4c /* RES current count */
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#define AD_DMA_ADCBA 0x50 /* ADC */
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#define AD_DMA_ADCCA 0x54
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#define AD_DMA_ADCBC 0x58
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#define AD_DMA_ADCCC 0x5c
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#define AD_DMA_SYNBA 0x60 /* SYN */
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#define AD_DMA_SYNCA 0x64
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#define AD_DMA_SYNBC 0x68
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#define AD_DMA_SYNCC 0x6c
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#define AD_DMA_WAVBA 0x70 /* WAV */
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#define AD_DMA_WAVCA 0x74
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#define AD_DMA_WAVBC 0x78
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#define AD_DMA_WAVCC 0x7c
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#define AD_DMA_RESICC 0x80 /* RES interrupt current count */
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#define AD_DMA_RESIBC 0x84 /* RES interrupt base count */
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#define AD_DMA_ADCICC 0x88 /* ADC interrupt current count */
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#define AD_DMA_ADCIBC 0x8c /* ADC interrupt base count */
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#define AD_DMA_SYNICC 0x90 /* SYN interrupt current count */
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#define AD_DMA_SYNIBC 0x94 /* SYN interrupt base count */
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#define AD_DMA_WAVICC 0x98 /* WAV interrupt current count */
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#define AD_DMA_WAVIBC 0x9c /* WAV interrupt base count */
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#define AD_DMA_RESCTRL 0xa0 /* RES PCI control/status */
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#define AD_DMA_ADCCTRL 0xa8 /* ADC PCI control/status */
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#define AD_DMA_SYNCTRL 0xb0 /* SYN PCI control/status */
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#define AD_DMA_WAVCTRL 0xb8 /* WAV PCI control/status */
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#define AD_DMA_DISR 0xc0 /* PCI DMA intr status */
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#define AD_DMA_CHSS 0xc4 /* PCI DMA channel stop status */
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#define AD_GPIO_IPC 0xc8 /* IO port ctrl */
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#define AD_GPIO_OP 0xca /* IO output status */
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#define AD_GPIO_IP 0xcc /* IO input status */
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/* AC97 registers, 0x100 - 0x17f; see ac97.h */
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#define AD_AC97_BASE 0x100 /* ac97 base register */
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#define AD_AC97_ACIC 0x180 /* AC Link interface ctrl */
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/* OPL3; BAR1 */
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#define AD_OPL_M0AS 0x00 /* Music0 address/status */
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#define AD_OPL_M0DATA 0x01 /* Music0 data */
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#define AD_OPL_M1A 0x02 /* Music1 address */
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#define AD_OPL_M1DATA 0x03 /* Music1 data */
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/* 0x04-0x0f reserved */
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/* MIDI; BAR2 */
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#define AD_MIDA 0x00 /* MIDI data */
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#define AD_MISC 0x01 /* MIDI status/cmd */
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/* 0x02-0xff reserved */
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#define AD_DS_IOMEMSIZE 512
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#define AD_OPL_MEMSIZE 16
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#define AD_MIDI_MEMSIZE 16
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#define AD_WAV_STATE 0
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#define AD_ADC_STATE 1
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#define AD_MAX_STATES 2
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#define DMA_SIZE (128*1024)
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#define DMA_FLAG_MAPPED 1
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struct ad1889_dev;
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typedef struct ad1889_state {
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struct ad1889_dev *card;
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mode_t open_mode;
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struct dmabuf {
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unsigned int rate;
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unsigned char fmt, enable;
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/* buf management */
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size_t rawbuf_size;
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void *rawbuf;
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dma_addr_t dma_handle; /* mapped address */
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unsigned long dma_len; /* number of bytes mapped */
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/* indexes into rawbuf for setting up DMA engine */
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volatile unsigned long rd_ptr, wr_ptr;
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wait_queue_head_t wait; /* to wait for buf servicing */
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/* OSS bits */
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unsigned int mapped:1;
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unsigned int ready:1;
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unsigned int ossfragshift;
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int ossmaxfrags;
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unsigned int subdivision;
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} dmabuf;
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struct mutex mutex;
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} ad1889_state_t;
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typedef struct ad1889_dev {
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void __iomem *regbase;
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struct pci_dev *pci;
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spinlock_t lock;
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int dev_audio;
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/* states; one per channel; right now only WAV and ADC */
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struct ad1889_state state[AD_MAX_STATES];
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/* AC97 codec */
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struct ac97_codec *ac97_codec;
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u16 ac97_features;
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/* debugging stuff */
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struct stats {
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unsigned int wav_intrs, adc_intrs;
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unsigned int blocks, underrun, error;
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} stats;
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} ad1889_dev_t;
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typedef struct ad1889_reg {
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const char *name;
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int offset;
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int width;
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} ad1889_reg_t;
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#endif
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