1135 lines
24 KiB
C
1135 lines
24 KiB
C
/*
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* Clock manipulation routines for Freescale STMP37XX/STMP378X
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*
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* Author: Vitaly Wool <vital@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <asm/clkdev.h>
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#include <mach/platform.h>
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#include <mach/regs-clkctrl.h>
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#include "clock.h"
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static DEFINE_SPINLOCK(clocks_lock);
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static struct clk osc_24M;
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static struct clk pll_clk;
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static struct clk cpu_clk;
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static struct clk hclk;
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static int propagate_rate(struct clk *);
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static inline int clk_is_busy(struct clk *clk)
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{
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return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
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}
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static inline int clk_good(struct clk *clk)
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{
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return clk && !IS_ERR(clk) && clk->ops;
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}
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static int std_clk_enable(struct clk *clk)
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{
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if (clk->enable_reg) {
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u32 clk_reg = __raw_readl(clk->enable_reg);
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if (clk->enable_negate)
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clk_reg &= ~(1 << clk->enable_shift);
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else
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clk_reg |= (1 << clk->enable_shift);
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__raw_writel(clk_reg, clk->enable_reg);
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if (clk->enable_wait)
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udelay(clk->enable_wait);
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return 0;
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} else
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return -EINVAL;
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}
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static int std_clk_disable(struct clk *clk)
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{
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if (clk->enable_reg) {
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u32 clk_reg = __raw_readl(clk->enable_reg);
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if (clk->enable_negate)
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clk_reg |= (1 << clk->enable_shift);
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else
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clk_reg &= ~(1 << clk->enable_shift);
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__raw_writel(clk_reg, clk->enable_reg);
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return 0;
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} else
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return -EINVAL;
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}
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static int io_set_rate(struct clk *clk, u32 rate)
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{
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u32 reg_frac, clkctrl_frac;
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int i, ret = 0, mask = 0x1f;
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clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
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if (clkctrl_frac < 18 || clkctrl_frac > 35) {
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ret = -EINVAL;
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goto out;
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}
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reg_frac = __raw_readl(clk->scale_reg);
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reg_frac &= ~(mask << clk->scale_shift);
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__raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
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clk->scale_reg);
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if (clk->busy_reg) {
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for (i = 10000; i; i--)
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if (!clk_is_busy(clk))
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break;
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if (!i)
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ret = -ETIMEDOUT;
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else
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ret = 0;
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}
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out:
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return ret;
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}
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static long io_get_rate(struct clk *clk)
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{
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long rate = clk->parent->rate * 18;
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int mask = 0x1f;
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rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
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clk->rate = rate;
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return rate;
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}
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static long per_get_rate(struct clk *clk)
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{
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long rate = clk->parent->rate;
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long div;
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const int mask = 0xff;
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if (clk->enable_reg &&
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!(__raw_readl(clk->enable_reg) & clk->enable_shift))
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clk->rate = 0;
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else {
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div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
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if (div)
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rate /= div;
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clk->rate = rate;
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}
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return clk->rate;
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}
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static int per_set_rate(struct clk *clk, u32 rate)
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{
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int ret = -EINVAL;
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int div = (clk->parent->rate + rate - 1) / rate;
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u32 reg_frac;
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const int mask = 0xff;
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int try = 10;
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int i = -1;
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if (div == 0 || div > mask)
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goto out;
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reg_frac = __raw_readl(clk->scale_reg);
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reg_frac &= ~(mask << clk->scale_shift);
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while (try--) {
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__raw_writel(reg_frac | (div << clk->scale_shift),
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clk->scale_reg);
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if (clk->busy_reg) {
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for (i = 10000; i; i--)
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if (!clk_is_busy(clk))
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break;
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}
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if (i)
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break;
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}
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if (!i)
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ret = -ETIMEDOUT;
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else
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ret = 0;
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out:
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if (ret != 0)
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printk(KERN_ERR "%s: error %d\n", __func__, ret);
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return ret;
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}
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static long lcdif_get_rate(struct clk *clk)
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{
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long rate = clk->parent->rate;
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long div;
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const int mask = 0xff;
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div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
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if (div) {
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rate /= div;
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div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
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rate /= div;
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}
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clk->rate = rate;
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return rate;
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}
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static int lcdif_set_rate(struct clk *clk, u32 rate)
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{
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int ret = 0;
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/*
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* On 3700, we can get most timings exact by modifying ref_pix
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* and the divider, but keeping the phase timings at 1 (2
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* phases per cycle).
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*
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* ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
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* which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
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*
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* ns_cycle >= 2*18e3/(18*480) = 25/6
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* ns_cycle <= 2*35e3/(18*480) = 875/108
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*
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* Multiply the ns_cycle by 'div' to lengthen it until it fits the
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* bounds. This is the divider we'll use after ref_pix.
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*
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* 6 * ns_cycle >= 25 * div
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* 108 * ns_cycle <= 875 * div
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*/
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u32 ns_cycle = 1000000 / rate;
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u32 div, reg_val;
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u32 lowest_result = (u32) -1;
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u32 lowest_div = 0, lowest_fracdiv = 0;
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for (div = 1; div < 256; ++div) {
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u32 fracdiv;
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u32 ps_result;
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int lower_bound = 6 * ns_cycle >= 25 * div;
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int upper_bound = 108 * ns_cycle <= 875 * div;
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if (!lower_bound)
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break;
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if (!upper_bound)
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continue;
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/*
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* Found a matching div. Calculate fractional divider needed,
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* rounded up.
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*/
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fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
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ns_cycle + 1000 * div - 1) /
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(1000 * div);
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if (fracdiv < 18 || fracdiv > 35) {
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ret = -EINVAL;
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goto out;
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}
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/* Calculate the actual cycle time this results in */
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ps_result = 6250 * div * fracdiv / 27;
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/* Use the fastest result that doesn't break ns_cycle */
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if (ps_result <= lowest_result) {
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lowest_result = ps_result;
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lowest_div = div;
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lowest_fracdiv = fracdiv;
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}
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}
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if (div >= 256 || lowest_result == (u32) -1) {
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ret = -EINVAL;
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goto out;
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}
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pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
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"PIXCLK=%uMHz cycle=%u.%03uns\n",
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lowest_fracdiv, lowest_div,
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480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
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lowest_result / 1000, lowest_result % 1000);
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/* Program ref_pix phase fractional divider */
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reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
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reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
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reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
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__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
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/* Ungate PFD */
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stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
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REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
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/* Program pix divider */
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reg_val = __raw_readl(clk->scale_reg);
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reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
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reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
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__raw_writel(reg_val, clk->scale_reg);
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/* Wait for divider update */
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if (clk->busy_reg) {
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int i;
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for (i = 10000; i; i--)
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if (!clk_is_busy(clk))
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break;
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if (!i) {
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ret = -ETIMEDOUT;
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goto out;
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}
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}
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/* Switch to ref_pix source */
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reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
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reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
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__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
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out:
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return ret;
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}
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static int cpu_set_rate(struct clk *clk, u32 rate)
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{
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u32 reg_val;
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if (rate < 24000)
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return -EINVAL;
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else if (rate == 24000) {
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/* switch to the 24M source */
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clk_set_parent(clk, &osc_24M);
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} else {
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int i;
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u32 clkctrl_cpu = 1;
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u32 c = clkctrl_cpu;
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u32 clkctrl_frac = 1;
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u32 val;
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for ( ; c < 0x40; c++) {
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u32 f = (pll_clk.rate*18/c + rate/2) / rate;
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int s1, s2;
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if (f < 18 || f > 35)
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continue;
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s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
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s2 = pll_clk.rate*18/c/f - rate;
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pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
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if (abs(s1) > abs(s2)) {
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clkctrl_cpu = c;
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clkctrl_frac = f;
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}
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if (s2 == 0)
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break;
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};
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pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
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clkctrl_cpu, clkctrl_frac);
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if (c == 0x40) {
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int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
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rate;
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if (abs(d) > 100 ||
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clkctrl_frac < 18 || clkctrl_frac > 35)
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return -EINVAL;
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}
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/* 4.6.2 */
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val = __raw_readl(clk->scale_reg);
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val &= ~(0x3f << clk->scale_shift);
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val |= clkctrl_frac;
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clk_set_parent(clk, &osc_24M);
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udelay(10);
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__raw_writel(val, clk->scale_reg);
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/* ungate */
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__raw_writel(1<<7, clk->scale_reg + 8);
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/* write clkctrl_cpu */
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clk->saved_div = clkctrl_cpu;
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reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
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reg_val &= ~0x3F;
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reg_val |= clkctrl_cpu;
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__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
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for (i = 10000; i; i--)
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if (!clk_is_busy(clk))
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break;
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if (!i) {
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printk(KERN_ERR "couldn't set up CPU divisor\n");
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return -ETIMEDOUT;
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}
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clk_set_parent(clk, &pll_clk);
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clk->saved_div = 0;
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udelay(10);
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}
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return 0;
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}
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static long cpu_get_rate(struct clk *clk)
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{
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long rate = clk->parent->rate * 18;
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rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
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rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
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rate = ((rate + 9) / 10) * 10;
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clk->rate = rate;
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return rate;
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}
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static long cpu_round_rate(struct clk *clk, u32 rate)
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{
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unsigned long r = 0;
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if (rate <= 24000)
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r = 24000;
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else {
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u32 clkctrl_cpu = 1;
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u32 clkctrl_frac;
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do {
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clkctrl_frac =
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(pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
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if (clkctrl_frac > 35)
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continue;
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if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
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rate / 10)
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break;
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} while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
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if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
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clkctrl_cpu--;
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pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
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clkctrl_cpu, clkctrl_frac);
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if (clkctrl_frac < 18)
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clkctrl_frac = 18;
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if (clkctrl_frac > 35)
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clkctrl_frac = 35;
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r = pll_clk.rate * 18;
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r /= clkctrl_frac;
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r /= clkctrl_cpu;
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r = 10 * ((r + 9) / 10);
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}
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return r;
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}
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static long emi_get_rate(struct clk *clk)
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{
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long rate = clk->parent->rate * 18;
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rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
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rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
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clk->rate = rate;
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return rate;
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}
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static int clkseq_set_parent(struct clk *clk, struct clk *parent)
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{
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int ret = -EINVAL;
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int shift = 8;
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/* bypass? */
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if (parent == &osc_24M)
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shift = 4;
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if (clk->bypass_reg) {
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#ifdef CONFIG_ARCH_STMP378X
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u32 hbus_val, cpu_val;
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if (clk == &cpu_clk && shift == 4) {
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hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
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HW_CLKCTRL_HBUS);
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cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
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HW_CLKCTRL_CPU);
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hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
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BM_CLKCTRL_HBUS_DIV);
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clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
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cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
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cpu_val |= 1;
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if (machine_is_stmp378x()) {
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__raw_writel(hbus_val,
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REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
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__raw_writel(cpu_val,
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REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
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hclk.rate = 0;
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}
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} else if (clk == &cpu_clk && shift == 8) {
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hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
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HW_CLKCTRL_HBUS);
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cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
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HW_CLKCTRL_CPU);
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hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
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BM_CLKCTRL_HBUS_DIV);
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hbus_val |= 2;
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cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
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if (clk->saved_div)
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cpu_val |= clk->saved_div;
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else
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cpu_val |= 2;
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if (machine_is_stmp378x()) {
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__raw_writel(hbus_val,
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REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
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__raw_writel(cpu_val,
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REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
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hclk.rate = 0;
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}
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}
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#endif
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__raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
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ret = 0;
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}
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return ret;
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}
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|
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static int hbus_set_rate(struct clk *clk, u32 rate)
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{
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u8 div = 0;
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int is_frac = 0;
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u32 clkctrl_hbus;
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struct clk *parent = clk->parent;
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pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
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parent->rate);
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if (rate > parent->rate)
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return -EINVAL;
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if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
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parent->rate / rate < 32) {
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pr_debug("%s: switching to fractional mode\n", __func__);
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is_frac = 1;
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}
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|
|
if (is_frac)
|
|
div = (32 * rate + parent->rate / 2) / parent->rate;
|
|
else
|
|
div = (parent->rate + rate - 1) / rate;
|
|
pr_debug("%s: div calculated is %d\n", __func__, div);
|
|
if (!div || div > 0x1f)
|
|
return -EINVAL;
|
|
|
|
clk_set_parent(&cpu_clk, &osc_24M);
|
|
udelay(10);
|
|
clkctrl_hbus = __raw_readl(clk->scale_reg);
|
|
clkctrl_hbus &= ~0x3f;
|
|
clkctrl_hbus |= div;
|
|
clkctrl_hbus |= (is_frac << 5);
|
|
|
|
__raw_writel(clkctrl_hbus, clk->scale_reg);
|
|
if (clk->busy_reg) {
|
|
int i;
|
|
for (i = 10000; i; i--)
|
|
if (!clk_is_busy(clk))
|
|
break;
|
|
if (!i) {
|
|
printk(KERN_ERR "couldn't set up CPU divisor\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
}
|
|
clk_set_parent(&cpu_clk, &pll_clk);
|
|
__raw_writel(clkctrl_hbus, clk->scale_reg);
|
|
udelay(10);
|
|
return 0;
|
|
}
|
|
|
|
static long hbus_get_rate(struct clk *clk)
|
|
{
|
|
long rate = clk->parent->rate;
|
|
|
|
if (__raw_readl(clk->scale_reg) & 0x20) {
|
|
rate *= __raw_readl(clk->scale_reg) & 0x1f;
|
|
rate /= 32;
|
|
} else
|
|
rate /= __raw_readl(clk->scale_reg) & 0x1f;
|
|
clk->rate = rate;
|
|
|
|
return rate;
|
|
}
|
|
|
|
static int xbus_set_rate(struct clk *clk, u32 rate)
|
|
{
|
|
u16 div = 0;
|
|
u32 clkctrl_xbus;
|
|
|
|
pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
|
|
clk->parent->rate);
|
|
|
|
div = (clk->parent->rate + rate - 1) / rate;
|
|
pr_debug("%s: div calculated is %d\n", __func__, div);
|
|
if (!div || div > 0x3ff)
|
|
return -EINVAL;
|
|
|
|
clkctrl_xbus = __raw_readl(clk->scale_reg);
|
|
clkctrl_xbus &= ~0x3ff;
|
|
clkctrl_xbus |= div;
|
|
__raw_writel(clkctrl_xbus, clk->scale_reg);
|
|
if (clk->busy_reg) {
|
|
int i;
|
|
for (i = 10000; i; i--)
|
|
if (!clk_is_busy(clk))
|
|
break;
|
|
if (!i) {
|
|
printk(KERN_ERR "couldn't set up xbus divisor\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static long xbus_get_rate(struct clk *clk)
|
|
{
|
|
long rate = clk->parent->rate;
|
|
|
|
rate /= __raw_readl(clk->scale_reg) & 0x3ff;
|
|
clk->rate = rate;
|
|
|
|
return rate;
|
|
}
|
|
|
|
|
|
/* Clock ops */
|
|
|
|
static struct clk_ops std_ops = {
|
|
.enable = std_clk_enable,
|
|
.disable = std_clk_disable,
|
|
.get_rate = per_get_rate,
|
|
.set_rate = per_set_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
};
|
|
|
|
static struct clk_ops min_ops = {
|
|
.enable = std_clk_enable,
|
|
.disable = std_clk_disable,
|
|
};
|
|
|
|
static struct clk_ops cpu_ops = {
|
|
.enable = std_clk_enable,
|
|
.disable = std_clk_disable,
|
|
.get_rate = cpu_get_rate,
|
|
.set_rate = cpu_set_rate,
|
|
.round_rate = cpu_round_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
};
|
|
|
|
static struct clk_ops io_ops = {
|
|
.enable = std_clk_enable,
|
|
.disable = std_clk_disable,
|
|
.get_rate = io_get_rate,
|
|
.set_rate = io_set_rate,
|
|
};
|
|
|
|
static struct clk_ops hbus_ops = {
|
|
.get_rate = hbus_get_rate,
|
|
.set_rate = hbus_set_rate,
|
|
};
|
|
|
|
static struct clk_ops xbus_ops = {
|
|
.get_rate = xbus_get_rate,
|
|
.set_rate = xbus_set_rate,
|
|
};
|
|
|
|
static struct clk_ops lcdif_ops = {
|
|
.enable = std_clk_enable,
|
|
.disable = std_clk_disable,
|
|
.get_rate = lcdif_get_rate,
|
|
.set_rate = lcdif_set_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
};
|
|
|
|
static struct clk_ops emi_ops = {
|
|
.get_rate = emi_get_rate,
|
|
};
|
|
|
|
/* List of on-chip clocks */
|
|
|
|
static struct clk osc_24M = {
|
|
.flags = FIXED_RATE | ENABLED,
|
|
.rate = 24000,
|
|
};
|
|
|
|
static struct clk pll_clk = {
|
|
.parent = &osc_24M,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
|
|
.enable_shift = 16,
|
|
.enable_wait = 10,
|
|
.flags = FIXED_RATE | ENABLED,
|
|
.rate = 480000,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk cpu_clk = {
|
|
.parent = &pll_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
|
|
.scale_shift = 0,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 7,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
|
|
.busy_bit = 28,
|
|
.flags = RATE_PROPAGATES | ENABLED,
|
|
.ops = &cpu_ops,
|
|
};
|
|
|
|
static struct clk io_clk = {
|
|
.parent = &pll_clk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
|
|
.scale_shift = 24,
|
|
.flags = RATE_PROPAGATES | ENABLED,
|
|
.ops = &io_ops,
|
|
};
|
|
|
|
static struct clk hclk = {
|
|
.parent = &cpu_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 7,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
|
|
.busy_bit = 29,
|
|
.flags = RATE_PROPAGATES | ENABLED,
|
|
.ops = &hbus_ops,
|
|
};
|
|
|
|
static struct clk xclk = {
|
|
.parent = &osc_24M,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
|
|
.busy_bit = 31,
|
|
.flags = RATE_PROPAGATES | ENABLED,
|
|
.ops = &xbus_ops,
|
|
};
|
|
|
|
static struct clk uart_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.flags = ENABLED,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk audio_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 30,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk pwm_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 29,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk dri_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 28,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk digctl_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 27,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk timer_clk = {
|
|
.parent = &xclk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
|
|
.enable_shift = 26,
|
|
.enable_negate = 1,
|
|
.flags = ENABLED,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk lcdif_clk = {
|
|
.parent = &pll_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
|
|
.busy_bit = 29,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 1,
|
|
.flags = NEEDS_SET_PARENT,
|
|
.ops = &lcdif_ops,
|
|
};
|
|
|
|
static struct clk ssp_clk = {
|
|
.parent = &io_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
|
|
.busy_bit = 29,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
|
|
.enable_shift = 31,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 5,
|
|
.enable_negate = 1,
|
|
.flags = NEEDS_SET_PARENT,
|
|
.ops = &std_ops,
|
|
};
|
|
|
|
static struct clk gpmi_clk = {
|
|
.parent = &io_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
|
|
.busy_bit = 29,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 4,
|
|
.flags = NEEDS_SET_PARENT,
|
|
.ops = &std_ops,
|
|
};
|
|
|
|
static struct clk spdif_clk = {
|
|
.parent = &pll_clk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk emi_clk = {
|
|
.parent = &pll_clk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
|
|
.scale_shift = 8,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
|
|
.busy_bit = 28,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 6,
|
|
.flags = ENABLED,
|
|
.ops = &emi_ops,
|
|
};
|
|
|
|
static struct clk ir_clk = {
|
|
.parent = &io_clk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 3,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
static struct clk saif_clk = {
|
|
.parent = &pll_clk,
|
|
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
|
|
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
|
|
.busy_bit = 29,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
|
|
.enable_shift = 31,
|
|
.enable_negate = 1,
|
|
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_shift = 0,
|
|
.ops = &std_ops,
|
|
};
|
|
|
|
static struct clk usb_clk = {
|
|
.parent = &pll_clk,
|
|
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
|
|
.enable_shift = 18,
|
|
.enable_negate = 1,
|
|
.ops = &min_ops,
|
|
};
|
|
|
|
/* list of all the clocks */
|
|
static struct clk_lookup onchip_clks[] = {
|
|
{
|
|
.con_id = "osc_24M",
|
|
.clk = &osc_24M,
|
|
}, {
|
|
.con_id = "pll",
|
|
.clk = &pll_clk,
|
|
}, {
|
|
.con_id = "cpu",
|
|
.clk = &cpu_clk,
|
|
}, {
|
|
.con_id = "hclk",
|
|
.clk = &hclk,
|
|
}, {
|
|
.con_id = "xclk",
|
|
.clk = &xclk,
|
|
}, {
|
|
.con_id = "io",
|
|
.clk = &io_clk,
|
|
}, {
|
|
.con_id = "uart",
|
|
.clk = &uart_clk,
|
|
}, {
|
|
.con_id = "audio",
|
|
.clk = &audio_clk,
|
|
}, {
|
|
.con_id = "pwm",
|
|
.clk = &pwm_clk,
|
|
}, {
|
|
.con_id = "dri",
|
|
.clk = &dri_clk,
|
|
}, {
|
|
.con_id = "digctl",
|
|
.clk = &digctl_clk,
|
|
}, {
|
|
.con_id = "timer",
|
|
.clk = &timer_clk,
|
|
}, {
|
|
.con_id = "lcdif",
|
|
.clk = &lcdif_clk,
|
|
}, {
|
|
.con_id = "ssp",
|
|
.clk = &ssp_clk,
|
|
}, {
|
|
.con_id = "gpmi",
|
|
.clk = &gpmi_clk,
|
|
}, {
|
|
.con_id = "spdif",
|
|
.clk = &spdif_clk,
|
|
}, {
|
|
.con_id = "emi",
|
|
.clk = &emi_clk,
|
|
}, {
|
|
.con_id = "ir",
|
|
.clk = &ir_clk,
|
|
}, {
|
|
.con_id = "saif",
|
|
.clk = &saif_clk,
|
|
}, {
|
|
.con_id = "usb",
|
|
.clk = &usb_clk,
|
|
},
|
|
};
|
|
|
|
static int __init propagate_rate(struct clk *clk)
|
|
{
|
|
struct clk_lookup *cl;
|
|
|
|
for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
|
|
cl++) {
|
|
if (unlikely(!clk_good(cl->clk)))
|
|
continue;
|
|
if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
|
|
cl->clk->ops->get_rate(cl->clk);
|
|
if (cl->clk->flags & RATE_PROPAGATES)
|
|
propagate_rate(cl->clk);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Exported API */
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
if (unlikely(!clk_good(clk)))
|
|
return 0;
|
|
|
|
if (clk->rate != 0)
|
|
return clk->rate;
|
|
|
|
if (clk->ops->get_rate != NULL)
|
|
return clk->ops->get_rate(clk);
|
|
|
|
return clk_get_rate(clk->parent);
|
|
}
|
|
EXPORT_SYMBOL(clk_get_rate);
|
|
|
|
long clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
if (unlikely(!clk_good(clk)))
|
|
return 0;
|
|
|
|
if (clk->ops->round_rate)
|
|
return clk->ops->round_rate(clk, rate);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(clk_round_rate);
|
|
|
|
static inline int close_enough(long rate1, long rate2)
|
|
{
|
|
return rate1 && !((rate2 - rate1) * 1000 / rate1);
|
|
}
|
|
|
|
int clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
if (unlikely(!clk_good(clk)))
|
|
goto out;
|
|
|
|
if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
|
|
goto out;
|
|
|
|
else if (!close_enough(clk->rate, rate)) {
|
|
ret = clk->ops->set_rate(clk, rate);
|
|
if (ret < 0)
|
|
goto out;
|
|
clk->rate = rate;
|
|
if (clk->flags & RATE_PROPAGATES)
|
|
propagate_rate(clk);
|
|
} else
|
|
ret = 0;
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_set_rate);
|
|
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
unsigned long clocks_flags;
|
|
|
|
if (unlikely(!clk_good(clk)))
|
|
return -EINVAL;
|
|
|
|
if (clk->parent)
|
|
clk_enable(clk->parent);
|
|
|
|
spin_lock_irqsave(&clocks_lock, clocks_flags);
|
|
|
|
clk->usage++;
|
|
if (clk->ops && clk->ops->enable)
|
|
clk->ops->enable(clk);
|
|
|
|
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(clk_enable);
|
|
|
|
static void local_clk_disable(struct clk *clk)
|
|
{
|
|
if (unlikely(!clk_good(clk)))
|
|
return;
|
|
|
|
if (clk->usage == 0 && clk->ops->disable)
|
|
clk->ops->disable(clk);
|
|
|
|
if (clk->parent)
|
|
local_clk_disable(clk->parent);
|
|
}
|
|
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
unsigned long clocks_flags;
|
|
|
|
if (unlikely(!clk_good(clk)))
|
|
return;
|
|
|
|
spin_lock_irqsave(&clocks_lock, clocks_flags);
|
|
|
|
if ((--clk->usage) == 0 && clk->ops->disable)
|
|
clk->ops->disable(clk);
|
|
|
|
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
|
|
if (clk->parent)
|
|
clk_disable(clk->parent);
|
|
}
|
|
EXPORT_SYMBOL(clk_disable);
|
|
|
|
/* Some additional API */
|
|
int clk_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
int ret = -ENODEV;
|
|
unsigned long clocks_flags;
|
|
|
|
if (unlikely(!clk_good(clk)))
|
|
goto out;
|
|
|
|
if (!clk->ops->set_parent)
|
|
goto out;
|
|
|
|
spin_lock_irqsave(&clocks_lock, clocks_flags);
|
|
|
|
ret = clk->ops->set_parent(clk, parent);
|
|
if (!ret) {
|
|
/* disable if usage count is 0 */
|
|
local_clk_disable(parent);
|
|
|
|
parent->usage += clk->usage;
|
|
clk->parent->usage -= clk->usage;
|
|
|
|
/* disable if new usage count is 0 */
|
|
local_clk_disable(clk->parent);
|
|
|
|
clk->parent = parent;
|
|
}
|
|
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_set_parent);
|
|
|
|
struct clk *clk_get_parent(struct clk *clk)
|
|
{
|
|
if (unlikely(!clk_good(clk)))
|
|
return NULL;
|
|
return clk->parent;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_parent);
|
|
|
|
static int __init clk_init(void)
|
|
{
|
|
struct clk_lookup *cl;
|
|
struct clk_ops *ops;
|
|
|
|
spin_lock_init(&clocks_lock);
|
|
|
|
for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
|
|
cl++) {
|
|
if (cl->clk->flags & ENABLED)
|
|
clk_enable(cl->clk);
|
|
else
|
|
local_clk_disable(cl->clk);
|
|
|
|
ops = cl->clk->ops;
|
|
|
|
if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
|
|
ops && ops->set_rate)
|
|
ops->set_rate(cl->clk, cl->clk->rate);
|
|
|
|
if (cl->clk->flags & FIXED_RATE) {
|
|
if (cl->clk->flags & RATE_PROPAGATES)
|
|
propagate_rate(cl->clk);
|
|
} else {
|
|
if (ops && ops->get_rate)
|
|
ops->get_rate(cl->clk);
|
|
}
|
|
|
|
if (cl->clk->flags & NEEDS_SET_PARENT) {
|
|
if (ops && ops->set_parent)
|
|
ops->set_parent(cl->clk, cl->clk->parent);
|
|
}
|
|
}
|
|
clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(clk_init);
|