linux-stable-rt/arch/mips/mm
Ralf Baechle 641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:05 +01:00
..
Makefile [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
c-r3k.c
c-r4k.c [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
c-tx39.c
cache.c [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
cerr-sb1.c [MIPS] SB1: Fix pile of gcc's bogus format string warnings. 2007-03-24 17:01:50 +00:00
cex-gen.S
cex-sb1.S
dma-default.c [MIPS] R10000: Fix wrong test in dma-default.c 2007-09-11 19:03:25 +01:00
extable.c
fault.c mm: fault feedback #2 2007-07-19 10:04:41 -07:00
highmem.c [MIPS] Remove LIMITED_DMA support 2007-05-11 14:28:31 +01:00
init.c [MIPS] Fix aliasing bug in copy_user_highpage. 2007-09-11 19:03:26 +01:00
ioremap.c Detach sched.h from mm.h 2007-05-21 09:18:19 -07:00
pg-r4k.c [MIPS] pg-r4k.c: Fix a typo in an R4600 v2 erratum workaround 2007-10-03 14:30:51 +01:00
pg-sb1.c [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
pgtable-32.c
pgtable-64.c
pgtable.c
sc-ip22.c
sc-mips.c
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 2007-07-10 17:33:02 +01:00
tlb-r8k.c
tlbex-fault.S
tlbex.c [MIPS] Add support for BCM47XX CPUs. 2007-10-11 23:46:02 +01:00