136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ATH_H
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#define ATH_H
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#include <linux/skbuff.h>
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#include <linux/if_ether.h>
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#include <net/mac80211.h>
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/*
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* The key cache is used for h/w cipher state and also for
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* tracking station state such as the current tx antenna.
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* We also setup a mapping table between key cache slot indices
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* and station state to short-circuit node lookups on rx.
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* Different parts have different size key caches. We handle
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* up to ATH_KEYMAX entries (could dynamically allocate state).
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*/
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#define ATH_KEYMAX 128 /* max key cache size we handle */
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static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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struct ath_ani {
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bool caldone;
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int16_t noise_floor;
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unsigned int longcal_timer;
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unsigned int shortcal_timer;
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unsigned int resetcal_timer;
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unsigned int checkani_timer;
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struct timer_list timer;
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};
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enum ath_device_state {
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ATH_HW_UNAVAILABLE,
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ATH_HW_INITIALIZED,
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};
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enum ath_bus_type {
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ATH_PCI,
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ATH_AHB,
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ATH_USB,
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};
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struct reg_dmn_pair_mapping {
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u16 regDmnEnum;
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u16 reg_5ghz_ctl;
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u16 reg_2ghz_ctl;
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};
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struct ath_regulatory {
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char alpha2[2];
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u16 country_code;
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u16 max_power_level;
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u32 tp_scale;
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u16 current_rd;
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u16 current_rd_ext;
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int16_t power_limit;
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struct reg_dmn_pair_mapping *regpair;
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};
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/**
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* struct ath_ops - Register read/write operations
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*
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* @read: Register read
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* @write: Register write
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* @enable_write_buffer: Enable multiple register writes
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* @disable_write_buffer: Disable multiple register writes
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* @write_flush: Flush buffered register writes
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*/
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struct ath_ops {
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unsigned int (*read)(void *, u32 reg_offset);
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void (*write)(void *, u32 val, u32 reg_offset);
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void (*enable_write_buffer)(void *);
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void (*disable_write_buffer)(void *);
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void (*write_flush) (void *);
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};
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struct ath_common;
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struct ath_bus_ops {
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enum ath_bus_type ath_bus_type;
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void (*read_cachesize)(struct ath_common *common, int *csz);
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bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
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void (*bt_coex_prep)(struct ath_common *common);
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};
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struct ath_common {
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void *ah;
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void *priv;
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struct ieee80211_hw *hw;
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int debug_mask;
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enum ath_device_state state;
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struct ath_ani ani;
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u16 cachelsz;
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u16 curaid;
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u8 macaddr[ETH_ALEN];
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u8 curbssid[ETH_ALEN];
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u8 bssidmask[ETH_ALEN];
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u8 tx_chainmask;
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u8 rx_chainmask;
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u32 rx_bufsize;
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u32 keymax;
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DECLARE_BITMAP(keymap, ATH_KEYMAX);
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u8 splitmic;
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struct ath_regulatory regulatory;
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const struct ath_ops *ops;
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const struct ath_bus_ops *bus_ops;
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};
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struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
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u32 len,
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gfp_t gfp_mask);
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void ath_hw_setbssidmask(struct ath_common *common);
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#endif /* ATH_H */
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