636 lines
13 KiB
C
636 lines
13 KiB
C
/*
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* linux/drivers/video/omap2/dss/dss.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "DSS"
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/seq_file.h>
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#include <linux/clk.h>
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#include <plat/display.h>
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#include "dss.h"
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#define DSS_BASE 0x48050000
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#define DSS_SZ_REGS SZ_512
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struct dss_reg {
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u16 idx;
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};
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#define DSS_REG(idx) ((const struct dss_reg) { idx })
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#define DSS_REVISION DSS_REG(0x0000)
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#define DSS_SYSCONFIG DSS_REG(0x0010)
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#define DSS_SYSSTATUS DSS_REG(0x0014)
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#define DSS_IRQSTATUS DSS_REG(0x0018)
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#define DSS_CONTROL DSS_REG(0x0040)
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#define DSS_SDI_CONTROL DSS_REG(0x0044)
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#define DSS_PLL_CONTROL DSS_REG(0x0048)
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#define DSS_SDI_STATUS DSS_REG(0x005C)
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#define REG_GET(idx, start, end) \
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FLD_GET(dss_read_reg(idx), start, end)
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#define REG_FLD_MOD(idx, val, start, end) \
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dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
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static struct {
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void __iomem *base;
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struct clk *dpll4_m4_ck;
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unsigned long cache_req_pck;
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unsigned long cache_prate;
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struct dss_clock_info cache_dss_cinfo;
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struct dispc_clock_info cache_dispc_cinfo;
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enum dss_clk_source dsi_clk_source;
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enum dss_clk_source dispc_clk_source;
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u32 ctx[DSS_SZ_REGS / sizeof(u32)];
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} dss;
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static int _omap_dss_wait_reset(void);
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static inline void dss_write_reg(const struct dss_reg idx, u32 val)
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{
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__raw_writel(val, dss.base + idx.idx);
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}
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static inline u32 dss_read_reg(const struct dss_reg idx)
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{
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return __raw_readl(dss.base + idx.idx);
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}
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#define SR(reg) \
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dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
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#define RR(reg) \
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dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
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void dss_save_context(void)
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{
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if (cpu_is_omap24xx())
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return;
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SR(SYSCONFIG);
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SR(CONTROL);
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#ifdef CONFIG_OMAP2_DSS_SDI
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SR(SDI_CONTROL);
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SR(PLL_CONTROL);
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#endif
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}
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void dss_restore_context(void)
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{
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if (_omap_dss_wait_reset())
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DSSERR("DSS not coming out of reset after sleep\n");
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RR(SYSCONFIG);
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RR(CONTROL);
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#ifdef CONFIG_OMAP2_DSS_SDI
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RR(SDI_CONTROL);
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RR(PLL_CONTROL);
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#endif
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}
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#undef SR
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#undef RR
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void dss_sdi_init(u8 datapairs)
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{
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u32 l;
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BUG_ON(datapairs > 3 || datapairs < 1);
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l = dss_read_reg(DSS_SDI_CONTROL);
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l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
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l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
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l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
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dss_write_reg(DSS_SDI_CONTROL, l);
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l = dss_read_reg(DSS_PLL_CONTROL);
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l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
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l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
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l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
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dss_write_reg(DSS_PLL_CONTROL, l);
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}
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int dss_sdi_enable(void)
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{
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unsigned long timeout;
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dispc_pck_free_enable(1);
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
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udelay(1); /* wait 2x PCLK */
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/* Lock SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
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/* Waiting for PLL lock request to complete */
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timeout = jiffies + msecs_to_jiffies(500);
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while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("PLL lock request timed out\n");
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goto err1;
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}
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}
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/* Clearing PLL_GO bit */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
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/* Waiting for PLL to lock */
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timeout = jiffies + msecs_to_jiffies(500);
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while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("PLL lock timed out\n");
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goto err1;
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}
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}
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dispc_lcd_enable_signal(1);
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/* Waiting for SDI reset to complete */
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timeout = jiffies + msecs_to_jiffies(500);
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while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("SDI reset timed out\n");
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goto err2;
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}
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}
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return 0;
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err2:
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dispc_lcd_enable_signal(0);
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err1:
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
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dispc_pck_free_enable(0);
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return -ETIMEDOUT;
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}
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void dss_sdi_disable(void)
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{
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dispc_lcd_enable_signal(0);
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dispc_pck_free_enable(0);
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
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}
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void dss_dump_clocks(struct seq_file *s)
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{
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unsigned long dpll4_ck_rate;
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unsigned long dpll4_m4_ck_rate;
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
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seq_printf(s, "- DSS -\n");
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seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
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if (cpu_is_omap3630())
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seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK1));
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else
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seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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dss_clk_get_rate(DSS_CLK_FCK1));
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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}
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void dss_dump_regs(struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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DUMPREG(DSS_REVISION);
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DUMPREG(DSS_SYSCONFIG);
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DUMPREG(DSS_SYSSTATUS);
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DUMPREG(DSS_IRQSTATUS);
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DUMPREG(DSS_CONTROL);
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DUMPREG(DSS_SDI_CONTROL);
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DUMPREG(DSS_PLL_CONTROL);
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DUMPREG(DSS_SDI_STATUS);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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#undef DUMPREG
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}
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void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
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{
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int b;
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BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
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clk_src != DSS_SRC_DSS1_ALWON_FCLK);
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b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
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REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
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dss.dispc_clk_source = clk_src;
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}
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void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
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{
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int b;
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BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
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clk_src != DSS_SRC_DSS1_ALWON_FCLK);
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b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
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REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
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dss.dsi_clk_source = clk_src;
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}
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enum dss_clk_source dss_get_dispc_clk_source(void)
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{
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return dss.dispc_clk_source;
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}
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enum dss_clk_source dss_get_dsi_clk_source(void)
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{
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return dss.dsi_clk_source;
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}
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/* calculate clock rates using dividers in cinfo */
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int dss_calc_clock_rates(struct dss_clock_info *cinfo)
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{
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unsigned long prate;
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if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
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cinfo->fck_div == 0)
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return -EINVAL;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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cinfo->fck = prate / cinfo->fck_div;
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return 0;
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}
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int dss_set_clock_div(struct dss_clock_info *cinfo)
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{
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unsigned long prate;
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int r;
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if (cpu_is_omap34xx()) {
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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DSSDBG("dpll4_m4 = %ld\n", prate);
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r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
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if (r)
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return r;
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}
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DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
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return 0;
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}
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int dss_get_clock_div(struct dss_clock_info *cinfo)
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{
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cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
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if (cpu_is_omap34xx()) {
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unsigned long prate;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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if (cpu_is_omap3630())
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cinfo->fck_div = prate / (cinfo->fck);
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else
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cinfo->fck_div = prate / (cinfo->fck / 2);
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} else {
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cinfo->fck_div = 0;
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}
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return 0;
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}
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unsigned long dss_get_dpll4_rate(void)
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{
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if (cpu_is_omap34xx())
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return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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else
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return 0;
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}
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int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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struct dss_clock_info *dss_cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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unsigned long prate;
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struct dss_clock_info best_dss;
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struct dispc_clock_info best_dispc;
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unsigned long fck;
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u16 fck_div;
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int match = 0;
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int min_fck_per_pck;
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prate = dss_get_dpll4_rate();
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fck = dss_clk_get_rate(DSS_CLK_FCK1);
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if (req_pck == dss.cache_req_pck &&
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((cpu_is_omap34xx() && prate == dss.cache_prate) ||
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dss.cache_dss_cinfo.fck == fck)) {
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DSSDBG("dispc clock info found from cache.\n");
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*dss_cinfo = dss.cache_dss_cinfo;
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*dispc_cinfo = dss.cache_dispc_cinfo;
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return 0;
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}
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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min_fck_per_pck = 0;
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}
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retry:
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memset(&best_dss, 0, sizeof(best_dss));
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memset(&best_dispc, 0, sizeof(best_dispc));
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if (cpu_is_omap24xx()) {
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struct dispc_clock_info cur_dispc;
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/* XXX can we change the clock on omap2? */
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fck = dss_clk_get_rate(DSS_CLK_FCK1);
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fck_div = 1;
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dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
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match = 1;
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best_dss.fck = fck;
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best_dss.fck_div = fck_div;
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best_dispc = cur_dispc;
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goto found;
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} else if (cpu_is_omap34xx()) {
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for (fck_div = (cpu_is_omap3630() ? 32 : 16);
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fck_div > 0; --fck_div) {
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struct dispc_clock_info cur_dispc;
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if (cpu_is_omap3630())
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fck = prate / fck_div;
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else
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fck = prate / fck_div * 2;
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if (fck > DISPC_MAX_FCK)
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continue;
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if (min_fck_per_pck &&
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fck < req_pck * min_fck_per_pck)
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continue;
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match = 1;
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dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
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if (abs(cur_dispc.pck - req_pck) <
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abs(best_dispc.pck - req_pck)) {
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best_dss.fck = fck;
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best_dss.fck_div = fck_div;
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best_dispc = cur_dispc;
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if (cur_dispc.pck == req_pck)
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goto found;
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}
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}
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} else {
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BUG();
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}
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found:
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if (!match) {
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if (min_fck_per_pck) {
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DSSERR("Could not find suitable clock settings.\n"
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"Turning FCK/PCK constraint off and"
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"trying again.\n");
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min_fck_per_pck = 0;
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goto retry;
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}
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DSSERR("Could not find suitable clock settings.\n");
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return -EINVAL;
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}
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if (dss_cinfo)
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*dss_cinfo = best_dss;
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if (dispc_cinfo)
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*dispc_cinfo = best_dispc;
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dss.cache_req_pck = req_pck;
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dss.cache_prate = prate;
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dss.cache_dss_cinfo = best_dss;
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dss.cache_dispc_cinfo = best_dispc;
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return 0;
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}
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static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
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{
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dispc_irq_handler();
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return IRQ_HANDLED;
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}
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static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
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{
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u32 irqstatus;
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irqstatus = dss_read_reg(DSS_IRQSTATUS);
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if (irqstatus & (1<<0)) /* DISPC_IRQ */
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dispc_irq_handler();
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#ifdef CONFIG_OMAP2_DSS_DSI
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if (irqstatus & (1<<1)) /* DSI_IRQ */
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dsi_irq_handler();
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#endif
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return IRQ_HANDLED;
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}
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static int _omap_dss_wait_reset(void)
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{
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int t = 0;
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while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
|
|
if (++t > 1000) {
|
|
DSSERR("soft reset failed\n");
|
|
return -ENODEV;
|
|
}
|
|
udelay(1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int _omap_dss_reset(void)
|
|
{
|
|
/* Soft reset */
|
|
REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
|
|
return _omap_dss_wait_reset();
|
|
}
|
|
|
|
void dss_set_venc_output(enum omap_dss_venc_type type)
|
|
{
|
|
int l = 0;
|
|
|
|
if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
|
|
l = 0;
|
|
else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
|
|
l = 1;
|
|
else
|
|
BUG();
|
|
|
|
/* venc out selection. 0 = comp, 1 = svideo */
|
|
REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
|
|
}
|
|
|
|
void dss_set_dac_pwrdn_bgz(bool enable)
|
|
{
|
|
REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
|
|
}
|
|
|
|
int dss_init(bool skip_init)
|
|
{
|
|
int r;
|
|
u32 rev;
|
|
|
|
dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
|
|
if (!dss.base) {
|
|
DSSERR("can't ioremap DSS\n");
|
|
r = -ENOMEM;
|
|
goto fail0;
|
|
}
|
|
|
|
if (!skip_init) {
|
|
/* disable LCD and DIGIT output. This seems to fix the synclost
|
|
* problem that we get, if the bootloader starts the DSS and
|
|
* the kernel resets it */
|
|
omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
|
|
|
|
/* We need to wait here a bit, otherwise we sometimes start to
|
|
* get synclost errors, and after that only power cycle will
|
|
* restore DSS functionality. I have no idea why this happens.
|
|
* And we have to wait _before_ resetting the DSS, but after
|
|
* enabling clocks.
|
|
*/
|
|
msleep(50);
|
|
|
|
_omap_dss_reset();
|
|
}
|
|
|
|
/* autoidle */
|
|
REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
|
|
|
|
/* Select DPLL */
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_VENC
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
|
|
#endif
|
|
|
|
r = request_irq(INT_24XX_DSS_IRQ,
|
|
cpu_is_omap24xx()
|
|
? dss_irq_handler_omap2
|
|
: dss_irq_handler_omap3,
|
|
0, "OMAP DSS", NULL);
|
|
|
|
if (r < 0) {
|
|
DSSERR("omap2 dss: request_irq failed\n");
|
|
goto fail1;
|
|
}
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
|
|
if (IS_ERR(dss.dpll4_m4_ck)) {
|
|
DSSERR("Failed to get dpll4_m4_ck\n");
|
|
r = PTR_ERR(dss.dpll4_m4_ck);
|
|
goto fail2;
|
|
}
|
|
}
|
|
|
|
dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
|
|
dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
|
|
|
|
dss_save_context();
|
|
|
|
rev = dss_read_reg(DSS_REVISION);
|
|
printk(KERN_INFO "OMAP DSS rev %d.%d\n",
|
|
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
|
|
return 0;
|
|
|
|
fail2:
|
|
free_irq(INT_24XX_DSS_IRQ, NULL);
|
|
fail1:
|
|
iounmap(dss.base);
|
|
fail0:
|
|
return r;
|
|
}
|
|
|
|
void dss_exit(void)
|
|
{
|
|
if (cpu_is_omap34xx())
|
|
clk_put(dss.dpll4_m4_ck);
|
|
|
|
free_irq(INT_24XX_DSS_IRQ, NULL);
|
|
|
|
iounmap(dss.base);
|
|
}
|
|
|