145 lines
5.0 KiB
C
145 lines
5.0 KiB
C
/******************************************************************
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* Copyright (c) 2000-2007 PMC-Sierra INC.
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*
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* This program is free software; you can redistribute it
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* and/or modify it under the terms of the GNU General
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* Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write to the Free
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* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
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* 02139, USA.
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*
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* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
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* SOFTWARE.
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*/
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#ifndef MSP_USB_H_
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#define MSP_USB_H_
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#ifdef CONFIG_MSP_HAS_DUAL_USB
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#define NUM_USB_DEVS 2
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#else
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#define NUM_USB_DEVS 1
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#endif
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/* Register spaces for USB host 0 */
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#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0)
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#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17)
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#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000)
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#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f)
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#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100)
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#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF)
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/* Register spaces for USB host 1 */
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#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0)
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#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17)
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#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000)
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#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f)
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#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100)
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#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff)
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/* USB Identification registers */
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struct msp_usbid_regs {
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u32 id; /* 0x0: Identification register */
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u32 hwgen; /* 0x4: General HW params */
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u32 hwhost; /* 0x8: Host HW params */
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u32 hwdev; /* 0xc: Device HW params */
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u32 hwtxbuf; /* 0x10: Tx buffer HW params */
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u32 hwrxbuf; /* 0x14: Rx buffer HW params */
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u32 reserved[26];
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u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
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u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
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u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
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u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
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};
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/* MSBus to AMBA registers */
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struct msp_mab_regs {
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u32 isr; /* 0x0: Interrupt status */
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u32 imr; /* 0x4: Interrupt mask */
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u32 thcr0; /* 0x8: Transaction header capture 0 */
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u32 thcr1; /* 0xc: Transaction header capture 1 */
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u32 int_stat; /* 0x10: Interrupt status summary */
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u32 phy_cfg; /* 0x14: USB phy config */
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};
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/* EHCI registers */
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struct msp_usbhs_regs {
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u32 hciver; /* 0x0: Version and offset to operational regs */
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u32 hcsparams; /* 0x4: Host control structural parameters */
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u32 hccparams; /* 0x8: Host control capability parameters */
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u32 reserved0[5];
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u32 dciver; /* 0x20: Device interface version */
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u32 dccparams; /* 0x24: Device control capability parameters */
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u32 reserved1[6];
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u32 cmd; /* 0x40: USB command */
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u32 sts; /* 0x44: USB status */
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u32 int_ena; /* 0x48: USB interrupt enable */
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u32 frindex; /* 0x4c: Frame index */
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u32 reserved3;
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union {
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struct {
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u32 flb_addr; /* 0x54: Frame list base address */
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u32 next_async_addr; /* 0x58: next asynchronous addr */
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u32 ttctrl; /* 0x5c: embedded transaction translator
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async buffer status */
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u32 burst_size; /* 0x60: Controller burst size */
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u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
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u32 reserved0[4];
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u32 endpt_nak; /* 0x78: Endpoint NAK */
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u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
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u32 cfg_flag; /* 0x80: Config flag */
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u32 port_sc1; /* 0x84: Port status & control 1 */
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u32 reserved1[7];
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u32 otgsc; /* 0xa4: OTG status & control */
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u32 mode; /* 0xa8: USB controller mode */
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} host;
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struct {
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u32 dev_addr; /* 0x54: Device address */
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u32 endpt_list_addr; /* 0x58: Endpoint list address */
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u32 reserved0[7];
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u32 endpt_nak; /* 0x74 */
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u32 endpt_nak_ctrl; /* 0x78 */
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u32 cfg_flag; /* 0x80 */
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u32 port_sc1; /* 0x84: Port status & control 1 */
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u32 reserved[7];
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u32 otgsc; /* 0xa4: OTG status & control */
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u32 mode; /* 0xa8: USB controller mode */
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u32 endpt_setup_stat; /* 0xac */
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u32 endpt_prime; /* 0xb0 */
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u32 endpt_flush; /* 0xb4 */
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u32 endpt_stat; /* 0xb8 */
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u32 endpt_complete; /* 0xbc */
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u32 endpt_ctrl0; /* 0xc0 */
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u32 endpt_ctrl1; /* 0xc4 */
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u32 endpt_ctrl2; /* 0xc8 */
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u32 endpt_ctrl3; /* 0xcc */
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} device;
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} u;
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};
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/*
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* Container for the more-generic platform_device.
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* This exists mainly as a way to map the non-standard register
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* spaces and make them accessible to the USB ISR.
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*/
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struct mspusb_device {
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struct msp_mab_regs __iomem *mab_regs;
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struct msp_usbid_regs __iomem *usbid_regs;
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struct msp_usbhs_regs __iomem *usbhs_regs;
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struct platform_device dev;
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};
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#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
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#define TO_HOST_ID(x) ((x) & 0x3)
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#endif /*MSP_USB_H_*/
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