249 lines
6.2 KiB
C
249 lines
6.2 KiB
C
/*
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* Copyright 2002 Andi Kleen, SuSE Labs.
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* Thanks to Ben LaHaise for precious feedback.
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*/
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <asm/uaccess.h>
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#include <asm/processor.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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pte_t *lookup_address(unsigned long address)
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{
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pgd_t *pgd = pgd_offset_k(address);
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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if (pgd_none(*pgd))
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return NULL;
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pud = pud_offset(pgd, address);
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if (!pud_present(*pud))
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return NULL;
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pmd = pmd_offset(pud, address);
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if (!pmd_present(*pmd))
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return NULL;
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if (pmd_large(*pmd))
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return (pte_t *)pmd;
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pte = pte_offset_kernel(pmd, address);
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if (pte && !pte_present(*pte))
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pte = NULL;
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return pte;
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}
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static struct page *split_large_page(unsigned long address, pgprot_t prot,
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pgprot_t ref_prot)
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{
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int i;
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unsigned long addr;
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struct page *base = alloc_pages(GFP_KERNEL, 0);
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pte_t *pbase;
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if (!base)
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return NULL;
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/*
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* page_private is used to track the number of entries in
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* the page table page have non standard attributes.
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*/
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SetPagePrivate(base);
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page_private(base) = 0;
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address = __pa(address);
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addr = address & LARGE_PAGE_MASK;
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pbase = (pte_t *)page_address(base);
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for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) {
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pbase[i] = pfn_pte(addr >> PAGE_SHIFT,
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addr == address ? prot : ref_prot);
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}
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return base;
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}
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static void cache_flush_page(void *adr)
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{
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int i;
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for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
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asm volatile("clflush (%0)" :: "r" (adr + i));
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}
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static void flush_kernel_map(void *arg)
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{
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struct list_head *l = (struct list_head *)arg;
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struct page *pg;
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/* When clflush is available always use it because it is
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much cheaper than WBINVD. */
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if (!cpu_has_clflush)
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asm volatile("wbinvd" ::: "memory");
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else list_for_each_entry(pg, l, lru) {
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void *adr = page_address(pg);
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cache_flush_page(adr);
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}
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__flush_tlb_all();
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}
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static inline void flush_map(struct list_head *l)
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{
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on_each_cpu(flush_kernel_map, l, 1, 1);
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}
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static LIST_HEAD(deferred_pages); /* protected by init_mm.mmap_sem */
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static inline void save_page(struct page *fpage)
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{
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if (!test_and_set_bit(PG_arch_1, &fpage->flags))
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list_add(&fpage->lru, &deferred_pages);
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}
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/*
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* No more special protections in this 2/4MB area - revert to a
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* large page again.
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*/
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static void revert_page(unsigned long address, pgprot_t ref_prot)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t large_pte;
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unsigned long pfn;
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pgd = pgd_offset_k(address);
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BUG_ON(pgd_none(*pgd));
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pud = pud_offset(pgd,address);
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BUG_ON(pud_none(*pud));
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pmd = pmd_offset(pud, address);
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BUG_ON(pmd_val(*pmd) & _PAGE_PSE);
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pfn = (__pa(address) & LARGE_PAGE_MASK) >> PAGE_SHIFT;
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large_pte = pfn_pte(pfn, ref_prot);
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large_pte = pte_mkhuge(large_pte);
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set_pte((pte_t *)pmd, large_pte);
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}
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static int
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__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot,
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pgprot_t ref_prot)
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{
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pte_t *kpte;
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struct page *kpte_page;
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pgprot_t ref_prot2;
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kpte = lookup_address(address);
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if (!kpte) return 0;
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kpte_page = virt_to_page(((unsigned long)kpte) & PAGE_MASK);
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BUG_ON(PageLRU(kpte_page));
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BUG_ON(PageCompound(kpte_page));
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if (pgprot_val(prot) != pgprot_val(ref_prot)) {
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if (!pte_huge(*kpte)) {
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set_pte(kpte, pfn_pte(pfn, prot));
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} else {
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/*
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* split_large_page will take the reference for this
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* change_page_attr on the split page.
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*/
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struct page *split;
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ref_prot2 = pte_pgprot(pte_clrhuge(*kpte));
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split = split_large_page(address, prot, ref_prot2);
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if (!split)
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return -ENOMEM;
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set_pte(kpte, mk_pte(split, ref_prot2));
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kpte_page = split;
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}
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page_private(kpte_page)++;
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} else if (!pte_huge(*kpte)) {
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set_pte(kpte, pfn_pte(pfn, ref_prot));
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BUG_ON(page_private(kpte_page) == 0);
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page_private(kpte_page)--;
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} else
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BUG();
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/* on x86-64 the direct mapping set at boot is not using 4k pages */
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BUG_ON(PageReserved(kpte_page));
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save_page(kpte_page);
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if (page_private(kpte_page) == 0)
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revert_page(address, ref_prot);
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return 0;
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}
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/*
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* Change the page attributes of an page in the linear mapping.
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*
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* This should be used when a page is mapped with a different caching policy
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* than write-back somewhere - some CPUs do not like it when mappings with
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* different caching policies exist. This changes the page attributes of the
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* in kernel linear mapping too.
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*
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* The caller needs to ensure that there are no conflicting mappings elsewhere.
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* This function only deals with the kernel linear map.
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*
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* Caller must call global_flush_tlb() after this.
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*/
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int change_page_attr_addr(unsigned long address, int numpages, pgprot_t prot)
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{
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int err = 0, kernel_map = 0;
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int i;
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if (address >= __START_KERNEL_map
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&& address < __START_KERNEL_map + KERNEL_TEXT_SIZE) {
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address = (unsigned long)__va(__pa(address));
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kernel_map = 1;
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}
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down_write(&init_mm.mmap_sem);
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for (i = 0; i < numpages; i++, address += PAGE_SIZE) {
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unsigned long pfn = __pa(address) >> PAGE_SHIFT;
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if (!kernel_map || pte_present(pfn_pte(0, prot))) {
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err = __change_page_attr(address, pfn, prot, PAGE_KERNEL);
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if (err)
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break;
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}
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/* Handle kernel mapping too which aliases part of the
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* lowmem */
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if (__pa(address) < KERNEL_TEXT_SIZE) {
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unsigned long addr2;
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pgprot_t prot2;
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addr2 = __START_KERNEL_map + __pa(address);
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/* Make sure the kernel mappings stay executable */
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prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot)));
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err = __change_page_attr(addr2, pfn, prot2,
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PAGE_KERNEL_EXEC);
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}
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}
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up_write(&init_mm.mmap_sem);
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return err;
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}
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/* Don't call this for MMIO areas that may not have a mem_map entry */
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int change_page_attr(struct page *page, int numpages, pgprot_t prot)
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{
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unsigned long addr = (unsigned long)page_address(page);
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return change_page_attr_addr(addr, numpages, prot);
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}
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void global_flush_tlb(void)
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{
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struct page *pg, *next;
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struct list_head l;
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down_read(&init_mm.mmap_sem);
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list_replace_init(&deferred_pages, &l);
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up_read(&init_mm.mmap_sem);
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flush_map(&l);
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list_for_each_entry_safe(pg, next, &l, lru) {
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list_del(&pg->lru);
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clear_bit(PG_arch_1, &pg->flags);
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if (page_private(pg) != 0)
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continue;
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ClearPagePrivate(pg);
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__free_page(pg);
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}
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}
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EXPORT_SYMBOL(change_page_attr);
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EXPORT_SYMBOL(global_flush_tlb);
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