465 lines
13 KiB
C
465 lines
13 KiB
C
/*
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* IBM PPC4xx DMA engine scatter/gather library
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*
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* Copyright 2002-2003 MontaVista Software Inc.
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*
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* Cleaned up and converted to new DCR access
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* Original code by Armin Kuster <akuster@mvista.com>
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* and Pete Popov <ppopov@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/ppc4xx_dma.h>
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void
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ppc4xx_set_sg_addr(int dmanr, phys_addr_t sg_addr)
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{
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_set_sg_addr: bad channel: %d\n", dmanr);
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return;
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}
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#ifdef PPC4xx_DMA_64BIT
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mtdcr(DCRN_ASGH0 + (dmanr * 0x8), (u32)(sg_addr >> 32));
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#endif
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mtdcr(DCRN_ASG0 + (dmanr * 0x8), (u32)sg_addr);
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}
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/*
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* Add a new sgl descriptor to the end of a scatter/gather list
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* which was created by alloc_dma_handle().
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*
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* For a memory to memory transfer, both dma addresses must be
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* valid. For a peripheral to memory transfer, one of the addresses
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* must be set to NULL, depending on the direction of the transfer:
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* memory to peripheral: set dst_addr to NULL,
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* peripheral to memory: set src_addr to NULL.
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*/
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int
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ppc4xx_add_dma_sgl(sgl_handle_t handle, phys_addr_t src_addr, phys_addr_t dst_addr,
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unsigned int count)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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ppc_dma_ch_t *p_dma_ch;
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if (!handle) {
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printk("ppc4xx_add_dma_sgl: null handle\n");
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return DMA_STATUS_BAD_HANDLE;
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}
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if (psgl->dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_add_dma_sgl: bad channel: %d\n", psgl->dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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p_dma_ch = &dma_channels[psgl->dmanr];
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#ifdef DEBUG_4xxDMA
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{
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int error = 0;
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unsigned int aligned =
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(unsigned) src_addr | (unsigned) dst_addr | count;
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switch (p_dma_ch->pwidth) {
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case PW_8:
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break;
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case PW_16:
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if (aligned & 0x1)
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error = 1;
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break;
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case PW_32:
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if (aligned & 0x3)
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error = 1;
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break;
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case PW_64:
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if (aligned & 0x7)
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error = 1;
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break;
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default:
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printk("ppc4xx_add_dma_sgl: invalid bus width: 0x%x\n",
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p_dma_ch->pwidth);
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return DMA_STATUS_GENERAL_ERROR;
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}
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if (error)
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printk
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("Alignment warning: ppc4xx_add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n",
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src_addr, dst_addr, count, p_dma_ch->pwidth);
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}
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#endif
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if ((unsigned) (psgl->ptail + 1) >= ((unsigned) psgl + SGL_LIST_SIZE)) {
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printk("sgl handle out of memory \n");
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return DMA_STATUS_OUT_OF_MEMORY;
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}
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if (!psgl->ptail) {
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psgl->phead = (ppc_sgl_t *)
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((unsigned) psgl + sizeof (sgl_list_info_t));
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psgl->phead_dma = psgl->dma_addr + sizeof(sgl_list_info_t);
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psgl->ptail = psgl->phead;
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psgl->ptail_dma = psgl->phead_dma;
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} else {
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if(p_dma_ch->int_on_final_sg) {
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/* mask out all dma interrupts, except error, on tail
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before adding new tail. */
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psgl->ptail->control_count &=
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~(SG_TCI_ENABLE | SG_ETI_ENABLE);
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}
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psgl->ptail->next = psgl->ptail_dma + sizeof(ppc_sgl_t);
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psgl->ptail++;
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psgl->ptail_dma += sizeof(ppc_sgl_t);
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}
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psgl->ptail->control = psgl->control;
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psgl->ptail->src_addr = src_addr;
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psgl->ptail->dst_addr = dst_addr;
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psgl->ptail->control_count = (count >> p_dma_ch->shift) |
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psgl->sgl_control;
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psgl->ptail->next = (uint32_t) NULL;
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return DMA_STATUS_GOOD;
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}
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/*
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* Enable (start) the DMA described by the sgl handle.
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*/
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void
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ppc4xx_enable_dma_sgl(sgl_handle_t handle)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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ppc_dma_ch_t *p_dma_ch;
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uint32_t sg_command;
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if (!handle) {
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printk("ppc4xx_enable_dma_sgl: null handle\n");
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return;
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} else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
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printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
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psgl->dmanr);
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return;
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} else if (!psgl->phead) {
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printk("ppc4xx_enable_dma_sgl: sg list empty\n");
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return;
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}
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p_dma_ch = &dma_channels[psgl->dmanr];
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psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */
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sg_command = mfdcr(DCRN_ASGC);
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ppc4xx_set_sg_addr(psgl->dmanr, psgl->phead_dma);
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sg_command |= SSG_ENABLE(psgl->dmanr);
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mtdcr(DCRN_ASGC, sg_command); /* start transfer */
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}
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/*
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* Halt an active scatter/gather DMA operation.
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*/
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void
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ppc4xx_disable_dma_sgl(sgl_handle_t handle)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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uint32_t sg_command;
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if (!handle) {
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printk("ppc4xx_enable_dma_sgl: null handle\n");
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return;
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} else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
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printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
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psgl->dmanr);
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return;
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}
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sg_command = mfdcr(DCRN_ASGC);
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sg_command &= ~SSG_ENABLE(psgl->dmanr);
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mtdcr(DCRN_ASGC, sg_command); /* stop transfer */
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}
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/*
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* Returns number of bytes left to be transferred from the entire sgl list.
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* *src_addr and *dst_addr get set to the source/destination address of
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* the sgl descriptor where the DMA stopped.
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*
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* An sgl transfer must NOT be active when this function is called.
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*/
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int
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ppc4xx_get_dma_sgl_residue(sgl_handle_t handle, phys_addr_t * src_addr,
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phys_addr_t * dst_addr)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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ppc_dma_ch_t *p_dma_ch;
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ppc_sgl_t *pnext, *sgl_addr;
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uint32_t count_left;
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if (!handle) {
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printk("ppc4xx_get_dma_sgl_residue: null handle\n");
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return DMA_STATUS_BAD_HANDLE;
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} else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
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printk("ppc4xx_get_dma_sgl_residue: bad channel in handle %d\n",
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psgl->dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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sgl_addr = (ppc_sgl_t *) __va(mfdcr(DCRN_ASG0 + (psgl->dmanr * 0x8)));
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count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8)) & SG_COUNT_MASK;
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if (!sgl_addr) {
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printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n");
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goto error;
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}
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pnext = psgl->phead;
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while (pnext &&
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((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) &&
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(pnext != sgl_addr))
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) {
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pnext++;
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}
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if (pnext == sgl_addr) { /* found the sgl descriptor */
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*src_addr = pnext->src_addr;
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*dst_addr = pnext->dst_addr;
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/*
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* Now search the remaining descriptors and add their count.
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* We already have the remaining count from this descriptor in
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* count_left.
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*/
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pnext++;
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while ((pnext != psgl->ptail) &&
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((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE))
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) {
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count_left += pnext->control_count & SG_COUNT_MASK;
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}
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if (pnext != psgl->ptail) { /* should never happen */
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printk
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("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n",
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(unsigned int) psgl->ptail, (unsigned int) handle);
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goto error;
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}
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/* success */
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p_dma_ch = &dma_channels[psgl->dmanr];
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return (count_left << p_dma_ch->shift); /* count in bytes */
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} else {
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/* this shouldn't happen */
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printk
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("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n",
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(unsigned int) sgl_addr, (unsigned int) handle);
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}
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error:
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*src_addr = (phys_addr_t) NULL;
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*dst_addr = (phys_addr_t) NULL;
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return 0;
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}
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/*
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* Returns the address(es) of the buffer(s) contained in the head element of
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* the scatter/gather list. The element is removed from the scatter/gather
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* list and the next element becomes the head.
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*
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* This function should only be called when the DMA is not active.
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*/
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int
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ppc4xx_delete_dma_sgl_element(sgl_handle_t handle, phys_addr_t * src_dma_addr,
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phys_addr_t * dst_dma_addr)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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if (!handle) {
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printk("ppc4xx_delete_sgl_element: null handle\n");
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return DMA_STATUS_BAD_HANDLE;
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} else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
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printk("ppc4xx_delete_sgl_element: bad channel in handle %d\n",
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psgl->dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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if (!psgl->phead) {
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printk("ppc4xx_delete_sgl_element: sgl list empty\n");
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*src_dma_addr = (phys_addr_t) NULL;
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*dst_dma_addr = (phys_addr_t) NULL;
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return DMA_STATUS_SGL_LIST_EMPTY;
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}
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*src_dma_addr = (phys_addr_t) psgl->phead->src_addr;
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*dst_dma_addr = (phys_addr_t) psgl->phead->dst_addr;
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if (psgl->phead == psgl->ptail) {
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/* last descriptor on the list */
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psgl->phead = NULL;
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psgl->ptail = NULL;
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} else {
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psgl->phead++;
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psgl->phead_dma += sizeof(ppc_sgl_t);
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}
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return DMA_STATUS_GOOD;
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}
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/*
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* Create a scatter/gather list handle. This is simply a structure which
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* describes a scatter/gather list.
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*
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* A handle is returned in "handle" which the driver should save in order to
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* be able to access this list later. A chunk of memory will be allocated
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* to be used by the API for internal management purposes, including managing
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* the sg list and allocating memory for the sgl descriptors. One page should
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* be more than enough for that purpose. Perhaps it's a bit wasteful to use
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* a whole page for a single sg list, but most likely there will be only one
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* sg list per channel.
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*
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* Interrupt notes:
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* Each sgl descriptor has a copy of the DMA control word which the DMA engine
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* loads in the control register. The control word has a "global" interrupt
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* enable bit for that channel. Interrupts are further qualified by a few bits
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* in the sgl descriptor count register. In order to setup an sgl, we have to
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* know ahead of time whether or not interrupts will be enabled at the completion
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* of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
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* be called before calling alloc_dma_handle(). If the interrupt mode will never
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* change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
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* do not have to be called -- interrupts will be enabled or disabled based
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* on how the channel was configured after powerup by the hw_init_dma_channel()
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* function. Each sgl descriptor will be setup to interrupt if an error occurs;
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* however, only the last descriptor will be setup to interrupt. Thus, an
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* interrupt will occur (if interrupts are enabled) only after the complete
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* sgl transfer is done.
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*/
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int
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ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
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{
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sgl_list_info_t *psgl=NULL;
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dma_addr_t dma_addr;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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uint32_t sg_command;
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uint32_t ctc_settings;
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void *ret;
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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if (!phandle) {
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printk("ppc4xx_alloc_dma_handle: null handle pointer\n");
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return DMA_STATUS_NULL_POINTER;
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}
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/* Get a page of memory, which is zeroed out by consistent_alloc() */
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ret = dma_alloc_coherent(NULL, DMA_PPC4xx_SIZE, &dma_addr, GFP_KERNEL);
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if (ret != NULL) {
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memset(ret, 0, DMA_PPC4xx_SIZE);
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psgl = (sgl_list_info_t *) ret;
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}
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if (psgl == NULL) {
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*phandle = (sgl_handle_t) NULL;
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return DMA_STATUS_OUT_OF_MEMORY;
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}
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psgl->dma_addr = dma_addr;
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psgl->dmanr = dmanr;
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/*
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* Modify and save the control word. These words will be
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* written to each sgl descriptor. The DMA engine then
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* loads this control word into the control register
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* every time it reads a new descriptor.
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*/
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psgl->control = p_dma_ch->control;
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/* Clear all mode bits */
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psgl->control &= ~(DMA_TM_MASK | DMA_TD);
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/* Save control word and mode */
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psgl->control |= (mode | DMA_CE_ENABLE);
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/* In MM mode, we must set ETD/TCE */
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if (mode == DMA_MODE_MM)
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psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
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if (p_dma_ch->int_enable) {
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/* Enable channel interrupt */
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psgl->control |= DMA_CIE_ENABLE;
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} else {
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psgl->control &= ~DMA_CIE_ENABLE;
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}
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sg_command = mfdcr(DCRN_ASGC);
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sg_command |= SSG_MASK_ENABLE(dmanr);
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/* Enable SGL control access */
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mtdcr(DCRN_ASGC, sg_command);
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psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
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/* keep control count register settings */
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ctc_settings = mfdcr(DCRN_DMACT0 + (dmanr * 0x8))
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& (DMA_CTC_BSIZ_MSK | DMA_CTC_BTEN); /*burst mode settings*/
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psgl->sgl_control |= ctc_settings;
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if (p_dma_ch->int_enable) {
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if (p_dma_ch->tce_enable)
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psgl->sgl_control |= SG_TCI_ENABLE;
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else
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psgl->sgl_control |= SG_ETI_ENABLE;
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}
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*phandle = (sgl_handle_t) psgl;
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return DMA_STATUS_GOOD;
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}
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/*
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* Destroy a scatter/gather list handle that was created by alloc_dma_handle().
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* The list must be empty (contain no elements).
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*/
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void
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ppc4xx_free_dma_handle(sgl_handle_t handle)
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{
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sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
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if (!handle) {
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printk("ppc4xx_free_dma_handle: got NULL\n");
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return;
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} else if (psgl->phead) {
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printk("ppc4xx_free_dma_handle: list not empty\n");
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return;
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} else if (!psgl->dma_addr) { /* should never happen */
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printk("ppc4xx_free_dma_handle: no dma address\n");
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return;
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}
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dma_free_coherent(NULL, DMA_PPC4xx_SIZE, (void *) psgl, 0);
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}
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EXPORT_SYMBOL(ppc4xx_alloc_dma_handle);
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EXPORT_SYMBOL(ppc4xx_free_dma_handle);
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EXPORT_SYMBOL(ppc4xx_add_dma_sgl);
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EXPORT_SYMBOL(ppc4xx_delete_dma_sgl_element);
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EXPORT_SYMBOL(ppc4xx_enable_dma_sgl);
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EXPORT_SYMBOL(ppc4xx_disable_dma_sgl);
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EXPORT_SYMBOL(ppc4xx_get_dma_sgl_residue);
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