579 lines
13 KiB
C
579 lines
13 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Synergy Microsystems board support by Dan Cox (dan@synergymicro.com)
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*
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/time.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/bcd.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/m48t35.h>
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#include <platforms/gemini.h>
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#include <asm/time.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/machdep.h>
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void gemini_find_bridges(void);
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static int gemini_get_clock_speed(void);
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extern void gemini_pcibios_fixup(void);
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static char *gemini_board_families[] = {
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"VGM", "VSS", "KGM", "VGR", "VCM", "VCS", "KCM", "VCR"
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};
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static int gemini_board_count = sizeof(gemini_board_families) /
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sizeof(gemini_board_families[0]);
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static unsigned int cpu_7xx[16] = {
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0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
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};
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static unsigned int cpu_6xx[16] = {
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0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
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};
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/*
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* prom_init is the Gemini version of prom.c:prom_init. We only need
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* the BSS clearing code, so I copied that out of prom.c. This is a
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* lot simpler than hacking prom.c so it will build with Gemini. -VAL
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*/
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#define PTRRELOC(x) ((typeof(x))((unsigned long)(x) + offset))
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unsigned long
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prom_init(void)
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{
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unsigned long offset = reloc_offset();
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unsigned long phys;
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extern char __bss_start, _end;
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/* First zero the BSS -- use memset, some arches don't have
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* caches on yet */
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memset_io(PTRRELOC(&__bss_start),0 , &_end - &__bss_start);
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/* Default */
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phys = offset + KERNELBASE;
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gemini_prom_init();
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return phys;
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}
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int
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gemini_show_cpuinfo(struct seq_file *m)
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{
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unsigned char reg, rev;
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char *family;
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unsigned int type;
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reg = readb(GEMINI_FEAT);
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family = gemini_board_families[((reg>>4) & 0xf)];
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if (((reg>>4) & 0xf) > gemini_board_count)
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printk(KERN_ERR "cpuinfo(): unable to determine board family\n");
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reg = readb(GEMINI_BREV);
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type = (reg>>4) & 0xf;
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rev = reg & 0xf;
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reg = readb(GEMINI_BECO);
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seq_printf(m, "machine\t\t: Gemini %s%d, rev %c, eco %d\n",
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family, type, (rev + 'A'), (reg & 0xf));
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seq_printf(m, "board\t\t: Gemini %s", family);
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if (type > 9)
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seq_printf(m, "%c", (type - 10) + 'A');
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else
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seq_printf(m, "%d", type);
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seq_printf(m, ", rev %c, eco %d\n", (rev + 'A'), (reg & 0xf));
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seq_printf(m, "clock\t\t: %dMhz\n", gemini_get_clock_speed());
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return 0;
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}
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static u_char gemini_openpic_initsenses[] = {
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1,
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1,
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1,
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1,
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0,
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0,
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1, /* remainder are level-triggered */
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};
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#define GEMINI_MPIC_ADDR (0xfcfc0000)
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#define GEMINI_MPIC_PCI_CFG (0x80005800)
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void __init gemini_openpic_init(void)
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{
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OpenPIC_Addr = (volatile struct OpenPIC *)
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grackle_read(GEMINI_MPIC_PCI_CFG + 0x10);
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OpenPIC_InitSenses = gemini_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof( gemini_openpic_initsenses );
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ioremap( GEMINI_MPIC_ADDR, OPENPIC_SIZE);
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}
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extern unsigned long loops_per_jiffy;
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extern int root_mountflags;
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extern char cmd_line[];
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void
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gemini_heartbeat(void)
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{
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static unsigned long led = GEMINI_LEDBASE+(4*8);
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static char direction = 8;
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/* We only want to do this on 1 CPU */
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if (smp_processor_id())
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return;
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*(char *)led = 0;
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if ( (led + direction) > (GEMINI_LEDBASE+(7*8)) ||
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(led + direction) < (GEMINI_LEDBASE+(4*8)) )
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direction *= -1;
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led += direction;
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*(char *)led = 0xff;
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ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
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}
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void __init gemini_setup_arch(void)
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{
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extern char cmd_line[];
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loops_per_jiffy = 50000000/HZ;
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#ifdef CONFIG_BLK_DEV_INITRD
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/* bootable off CDROM */
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if (initrd_start)
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ROOT_DEV = Root_SR0;
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else
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#endif
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ROOT_DEV = Root_SDA1;
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/* nothing but serial consoles... */
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sprintf(cmd_line, "%s console=ttyS0", cmd_line);
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printk("Boot arguments: %s\n", cmd_line);
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ppc_md.heartbeat = gemini_heartbeat;
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ppc_md.heartbeat_reset = HZ/8;
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ppc_md.heartbeat_count = 1;
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/* Lookup PCI hosts */
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gemini_find_bridges();
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/* take special pains to map the MPIC, since it isn't mapped yet */
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gemini_openpic_init();
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/* start the L2 */
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gemini_init_l2();
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}
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int
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gemini_get_clock_speed(void)
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{
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unsigned long hid1, pvr;
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int clock;
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pvr = mfspr(SPRN_PVR);
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hid1 = (mfspr(SPRN_HID1) >> 28) & 0xf;
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if (PVR_VER(pvr) == 8 ||
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PVR_VER(pvr) == 12)
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hid1 = cpu_7xx[hid1];
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else
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hid1 = cpu_6xx[hid1];
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switch((readb(GEMINI_BSTAT) & 0xc) >> 2) {
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case 0:
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default:
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clock = (hid1*100)/3;
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break;
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case 1:
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clock = (hid1*125)/3;
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break;
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case 2:
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clock = (hid1*50);
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break;
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}
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return clock;
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}
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void __init gemini_init_l2(void)
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{
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unsigned char reg, brev, fam, creg;
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unsigned long cache;
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unsigned long pvr;
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reg = readb(GEMINI_L2CFG);
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brev = readb(GEMINI_BREV);
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fam = readb(GEMINI_FEAT);
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pvr = mfspr(SPRN_PVR);
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switch(PVR_VER(pvr)) {
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case 8:
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if (reg & 0xc0)
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cache = (((reg >> 6) & 0x3) << 28);
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else
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cache = 0x3 << 28;
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#ifdef CONFIG_SMP
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/* Pre-3.0 processor revs had snooping errata. Leave
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their L2's disabled with SMP. -- Dan */
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if (PVR_CFG(pvr) < 3) {
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printk("Pre-3.0 750; L2 left disabled!\n");
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return;
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}
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#endif /* CONFIG_SMP */
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/* Special case: VGM5-B's came before L2 ratios were set on
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the board. Processor speed shouldn't be too high, so
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set L2 ratio to 1:1.5. */
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if ((brev == 0x51) && ((fam & 0xa0) >> 4) == 0)
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reg |= 1;
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/* determine best cache ratio based upon what the board
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tells us (which sometimes _may_ not be true) and
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the processor speed. */
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else {
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if (gemini_get_clock_speed() > 250)
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reg = 2;
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}
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break;
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case 12:
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{
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static unsigned long l2_size_val = 0;
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if (!l2_size_val)
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l2_size_val = _get_L2CR();
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cache = l2_size_val;
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break;
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}
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case 4:
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case 9:
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creg = readb(GEMINI_CPUSTAT);
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if (((creg & 0xc) >> 2) != 1)
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printk("Dual-604 boards don't support the use of L2\n");
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else
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writeb(1, GEMINI_L2CFG);
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return;
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default:
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printk("Unknown processor; L2 left disabled\n");
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return;
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}
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cache |= ((1<<reg) << 25);
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cache |= (L2CR_L2RAM_MASK|L2CR_L2CTL|L2CR_L2DO);
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_set_L2CR(0);
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_set_L2CR(cache | L2CR_L2E);
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}
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void
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gemini_restart(char *cmd)
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{
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local_irq_disable();
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/* make a clean restart, not via the MPIC */
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_gemini_reboot();
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for(;;);
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}
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void
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gemini_power_off(void)
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{
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for(;;);
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}
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void
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gemini_halt(void)
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{
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gemini_restart(NULL);
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}
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void __init gemini_init_IRQ(void)
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{
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/* gemini has no 8259 */
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openpic_init(1, 0, 0, -1);
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}
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#define gemini_rtc_read(x) (readb(GEMINI_RTC+(x)))
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#define gemini_rtc_write(val,x) (writeb((val),(GEMINI_RTC+(x))))
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/* ensure that the RTC is up and running */
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long __init gemini_time_init(void)
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{
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unsigned char reg;
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reg = gemini_rtc_read(M48T35_RTC_CONTROL);
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if ( reg & M48T35_RTC_STOPPED ) {
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printk(KERN_INFO "M48T35 real-time-clock was stopped. Now starting...\n");
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gemini_rtc_write((reg & ~(M48T35_RTC_STOPPED)), M48T35_RTC_CONTROL);
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gemini_rtc_write((reg | M48T35_RTC_SET), M48T35_RTC_CONTROL);
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}
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return 0;
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}
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#undef DEBUG_RTC
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unsigned long
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gemini_get_rtc_time(void)
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{
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unsigned int year, mon, day, hour, min, sec;
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unsigned char reg;
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reg = gemini_rtc_read(M48T35_RTC_CONTROL);
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gemini_rtc_write((reg|M48T35_RTC_READ), M48T35_RTC_CONTROL);
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#ifdef DEBUG_RTC
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printk("get rtc: reg = %x\n", reg);
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#endif
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do {
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sec = gemini_rtc_read(M48T35_RTC_SECONDS);
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min = gemini_rtc_read(M48T35_RTC_MINUTES);
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hour = gemini_rtc_read(M48T35_RTC_HOURS);
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day = gemini_rtc_read(M48T35_RTC_DOM);
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mon = gemini_rtc_read(M48T35_RTC_MONTH);
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year = gemini_rtc_read(M48T35_RTC_YEAR);
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} while( sec != gemini_rtc_read(M48T35_RTC_SECONDS));
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#ifdef DEBUG_RTC
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printk("get rtc: sec=%x, min=%x, hour=%x, day=%x, mon=%x, year=%x\n",
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sec, min, hour, day, mon, year);
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#endif
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gemini_rtc_write(reg, M48T35_RTC_CONTROL);
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BCD_TO_BIN(sec);
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BCD_TO_BIN(min);
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BCD_TO_BIN(hour);
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BCD_TO_BIN(day);
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BCD_TO_BIN(mon);
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BCD_TO_BIN(year);
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if ((year += 1900) < 1970)
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year += 100;
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#ifdef DEBUG_RTC
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printk("get rtc: sec=%x, min=%x, hour=%x, day=%x, mon=%x, year=%x\n",
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sec, min, hour, day, mon, year);
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#endif
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return mktime( year, mon, day, hour, min, sec );
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}
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int
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gemini_set_rtc_time( unsigned long now )
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{
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unsigned char reg;
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struct rtc_time tm;
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to_tm( now, &tm );
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reg = gemini_rtc_read(M48T35_RTC_CONTROL);
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#ifdef DEBUG_RTC
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printk("set rtc: reg = %x\n", reg);
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#endif
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gemini_rtc_write((reg|M48T35_RTC_SET), M48T35_RTC_CONTROL);
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#ifdef DEBUG_RTC
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printk("set rtc: tm vals - sec=%x, min=%x, hour=%x, mon=%x, mday=%x, year=%x\n",
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tm.tm_sec, tm.tm_min, tm.tm_hour, tm.tm_mon, tm.tm_mday, tm.tm_year);
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#endif
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tm.tm_year -= 1900;
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BIN_TO_BCD(tm.tm_sec);
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BIN_TO_BCD(tm.tm_min);
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BIN_TO_BCD(tm.tm_hour);
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BIN_TO_BCD(tm.tm_mon);
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BIN_TO_BCD(tm.tm_mday);
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BIN_TO_BCD(tm.tm_year);
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#ifdef DEBUG_RTC
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printk("set rtc: tm vals - sec=%x, min=%x, hour=%x, mon=%x, mday=%x, year=%x\n",
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tm.tm_sec, tm.tm_min, tm.tm_hour, tm.tm_mon, tm.tm_mday, tm.tm_year);
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#endif
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gemini_rtc_write(tm.tm_sec, M48T35_RTC_SECONDS);
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gemini_rtc_write(tm.tm_min, M48T35_RTC_MINUTES);
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gemini_rtc_write(tm.tm_hour, M48T35_RTC_HOURS);
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gemini_rtc_write(tm.tm_mday, M48T35_RTC_DOM);
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gemini_rtc_write(tm.tm_mon, M48T35_RTC_MONTH);
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gemini_rtc_write(tm.tm_year, M48T35_RTC_YEAR);
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/* done writing */
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gemini_rtc_write(reg, M48T35_RTC_CONTROL);
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return 0;
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}
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/* use the RTC to determine the decrementer count */
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void __init gemini_calibrate_decr(void)
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{
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int freq, divisor;
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unsigned char reg;
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/* determine processor bus speed */
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reg = readb(GEMINI_BSTAT);
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switch(((reg & 0x0c)>>2)&0x3) {
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case 0:
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default:
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freq = 66667;
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break;
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case 1:
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freq = 83000;
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break;
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case 2:
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freq = 100000;
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break;
|
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}
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freq *= 1000;
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divisor = 4;
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tb_ticks_per_jiffy = freq / HZ / divisor;
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tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
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}
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unsigned long __init gemini_find_end_of_memory(void)
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{
|
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unsigned long total;
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unsigned char reg;
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reg = readb(GEMINI_MEMCFG);
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total = ((1<<((reg & 0x7) - 1)) *
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(8<<((reg >> 3) & 0x7)));
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total *= (1024*1024);
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return total;
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}
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|
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static void __init
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gemini_map_io(void)
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{
|
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io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
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io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
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}
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|
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#ifdef CONFIG_SMP
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static int
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smp_gemini_probe(void)
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{
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int i, nr;
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nr = (readb(GEMINI_CPUSTAT) & GEMINI_CPU_COUNT_MASK) >> 2;
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if (nr == 0)
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nr = 4;
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if (nr > 1) {
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openpic_request_IPIs();
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for (i = 1; i < nr; ++i)
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smp_hw_index[i] = i;
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}
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return nr;
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}
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|
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static void
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smp_gemini_kick_cpu(int nr)
|
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{
|
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openpic_reset_processor_phys(1 << nr);
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openpic_reset_processor_phys(0);
|
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}
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|
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static void
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smp_gemini_setup_cpu(int cpu_nr)
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{
|
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if (OpenPIC_Addr)
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do_openpic_setup_cpu();
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if (cpu_nr > 0)
|
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gemini_init_l2();
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}
|
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|
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static struct smp_ops_t gemini_smp_ops = {
|
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smp_openpic_message_pass,
|
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smp_gemini_probe,
|
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smp_gemini_kick_cpu,
|
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smp_gemini_setup_cpu,
|
|
.give_timebase = smp_generic_give_timebase,
|
|
.take_timebase = smp_generic_take_timebase,
|
|
};
|
|
#endif /* CONFIG_SMP */
|
|
|
|
void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7)
|
|
{
|
|
int i;
|
|
|
|
/* Restore BATs for now */
|
|
mtspr(SPRN_DBAT3U, 0xf0001fff);
|
|
mtspr(SPRN_DBAT3L, 0xf000002a);
|
|
|
|
parse_bootinfo(find_bootinfo());
|
|
|
|
for(i = 0; i < GEMINI_LEDS; i++)
|
|
gemini_led_off(i);
|
|
|
|
ISA_DMA_THRESHOLD = 0;
|
|
DMA_MODE_READ = 0;
|
|
DMA_MODE_WRITE = 0;
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
if ( r4 )
|
|
{
|
|
initrd_start = r4 + KERNELBASE;
|
|
initrd_end = r5 + KERNELBASE;
|
|
}
|
|
#endif
|
|
|
|
ppc_md.setup_arch = gemini_setup_arch;
|
|
ppc_md.show_cpuinfo = gemini_show_cpuinfo;
|
|
ppc_md.init_IRQ = gemini_init_IRQ;
|
|
ppc_md.get_irq = openpic_get_irq;
|
|
ppc_md.init = NULL;
|
|
|
|
ppc_md.restart = gemini_restart;
|
|
ppc_md.power_off = gemini_power_off;
|
|
ppc_md.halt = gemini_halt;
|
|
|
|
ppc_md.time_init = gemini_time_init;
|
|
ppc_md.set_rtc_time = gemini_set_rtc_time;
|
|
ppc_md.get_rtc_time = gemini_get_rtc_time;
|
|
ppc_md.calibrate_decr = gemini_calibrate_decr;
|
|
|
|
ppc_md.find_end_of_memory = gemini_find_end_of_memory;
|
|
ppc_md.setup_io_mappings = gemini_map_io;
|
|
|
|
ppc_md.pcibios_fixup_bus = gemini_pcibios_fixup;
|
|
|
|
#ifdef CONFIG_SMP
|
|
smp_ops = &gemini_smp_ops;
|
|
#endif /* CONFIG_SMP */
|
|
}
|