46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* arch/i386/kernel/acpi/cstate.c
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*
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* Copyright (C) 2005 Intel Corporation
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* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* - Added _PDC for SMP C-states on Intel CPUs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <acpi/processor.h>
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#include <asm/acpi.h>
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/*
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* Initialize bm_flags based on the CPU cache properties
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* On SMP it depends on cache configuration
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* - When cache is not shared among all CPUs, we flush cache
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* before entering C3.
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* - When cache is shared among all CPUs, we use bm_check
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* mechanism as in UP case
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*
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* This routine is called only after all the CPUs are online
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*/
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void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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unsigned int cpu)
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{
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struct cpuinfo_x86 *c = cpu_data + cpu;
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flags->bm_check = 0;
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if (num_online_cpus() == 1)
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flags->bm_check = 1;
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else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Today all CPUs that support C3 share cache.
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* TBD: This needs to look at cache shared map, once
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* multi-core detection patch makes to the base.
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*/
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flags->bm_check = 1;
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}
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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