451 lines
9.2 KiB
ArmAsm
451 lines
9.2 KiB
ArmAsm
/* Boot entry point for MN10300 kernel
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*
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* Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <linux/serial_reg.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/frame.inc>
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#include <asm/param.h>
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#include <unit/serial.h>
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#ifdef CONFIG_SMP
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#include <asm/smp.h>
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#include <asm/intctl-regs.h>
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#include <asm/cpu-regs.h>
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#include <proc/smp-regs.h>
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#endif /* CONFIG_SMP */
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__HEAD
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###############################################################################
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#
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# bootloader entry point
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#
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###############################################################################
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.globl _start
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.type _start,@function
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_start:
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#ifdef CONFIG_SMP
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#
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# If this is a secondary CPU (AP), then deal with that elsewhere
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#
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mov (CPUID),d3
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and CPUID_MASK,d3
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bne startup_secondary
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#
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# We're dealing with the primary CPU (BP) here, then.
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# Keep BP's D0,D1,D2 register for boot check.
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#
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# Set up the Boot IPI for each secondary CPU
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mov 0x1,a0
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loop_set_secondary_icr:
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mov a0,a1
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asl CROSS_ICR_CPU_SHIFT,a1
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add CROSS_GxICR(SMP_BOOT_IRQ,0),a1
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movhu (a1),d3
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or GxICR_ENABLE|GxICR_LEVEL_0,d3
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movhu d3,(a1)
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movhu (a1),d3 # flush
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inc a0
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cmp NR_CPUS,a0
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bne loop_set_secondary_icr
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#endif /* CONFIG_SMP */
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# save commandline pointer
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mov d0,a3
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# preload the PGD pointer register
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mov swapper_pg_dir,d0
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mov d0,(PTBR)
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clr d0
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movbu d0,(PIDR)
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# turn on the TLBs
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mov MMUCTR_IIV|MMUCTR_DIV,d0
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mov d0,(MMUCTR)
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#ifdef CONFIG_AM34_2
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mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0
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#else
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mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
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#endif
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mov d0,(MMUCTR)
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# turn on AM33v2 exception handling mode and set the trap table base
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movhu (CPUP),d0
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or CPUP_EXM_AM33V2,d0
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movhu d0,(CPUP)
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mov CONFIG_INTERRUPT_VECTOR_BASE,d0
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mov d0,(TBR)
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# invalidate and enable both of the caches
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#ifdef CONFIG_SMP
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mov ECHCTR,a0
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clr d0
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mov d0,(a0)
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#endif
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mov CHCTR,a0
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clr d0
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movhu d0,(a0) # turn off first
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mov CHCTR_ICINV|CHCTR_DCINV,d0
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movhu d0,(a0)
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setlb
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mov (a0),d0
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btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
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lne
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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#ifdef CONFIG_MN10300_CACHE_WBACK
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#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
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#else
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0
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#endif /* NOWRALLOC */
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#else
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
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#endif /* WBACK */
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movhu d0,(a0) # enable
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#endif /* ENABLED */
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# turn on RTS on the debug serial port if applicable
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#ifdef CONFIG_MN10300_UNIT_ASB2305
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bset UART_MCR_RTS,(ASB2305_DEBUG_MCR)
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#endif
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# clear the BSS area
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mov __bss_start,a0
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mov __bss_stop,a1
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clr d0
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bssclear:
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cmp a1,a0
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bge bssclear_end
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mov d0,(a0)
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inc4 a0
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bra bssclear
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bssclear_end:
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# retrieve the parameters (including command line) before we overwrite
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# them
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cmp 0xabadcafe,d1
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bne __no_parameters
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__copy_parameters:
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mov redboot_command_line,a0
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mov a0,a1
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add COMMAND_LINE_SIZE,a1
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1:
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movbu (a3),d0
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inc a3
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movbu d0,(a0)
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inc a0
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cmp a1,a0
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blt 1b
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mov redboot_platform_name,a0
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mov a0,a1
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add COMMAND_LINE_SIZE,a1
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mov d2,a3
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1:
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movbu (a3),d0
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inc a3
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movbu d0,(a0)
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inc a0
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cmp a1,a0
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blt 1b
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__no_parameters:
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# set up the registers with recognisable rubbish in them
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mov init_thread_union+THREAD_SIZE-12,sp
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mov 0xea01eaea,d0
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mov d0,(4,sp) # EPSW save area
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mov 0xea02eaea,d0
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mov d0,(8,sp) # PC save area
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mov 0xeb0060ed,d0
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mov d0,mdr
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mov 0xeb0061ed,d0
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mov d0,mdrq
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mov 0xeb0062ed,d0
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mov d0,mcrh
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mov 0xeb0063ed,d0
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mov d0,mcrl
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mov 0xeb0064ed,d0
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mov d0,mcvf
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mov 0xed0065ed,a3
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mov a3,usp
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mov 0xed00e0ed,e0
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mov 0xed00e1ed,e1
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mov 0xed00e2ed,e2
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mov 0xed00e3ed,e3
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mov 0xed00e4ed,e4
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mov 0xed00e5ed,e5
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mov 0xed00e6ed,e6
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mov 0xed00e7ed,e7
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mov 0xed00d0ed,d0
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mov 0xed00d1ed,d1
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mov 0xed00d2ed,d2
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mov 0xed00d3ed,d3
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mov 0xed00a0ed,a0
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mov 0xed00a1ed,a1
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mov 0xed00a2ed,a2
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mov 0,a3
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# set up the initial kernel stack
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SAVE_ALL
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mov 0xffffffff,d0
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mov d0,(REG_ORIG_D0,fp)
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# put different recognisable rubbish in the regs
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mov 0xfb0060ed,d0
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mov d0,mdr
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mov 0xfb0061ed,d0
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mov d0,mdrq
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mov 0xfb0062ed,d0
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mov d0,mcrh
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mov 0xfb0063ed,d0
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mov d0,mcrl
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mov 0xfb0064ed,d0
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mov d0,mcvf
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mov 0xfd0065ed,a0
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mov a0,usp
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mov 0xfd00e0ed,e0
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mov 0xfd00e1ed,e1
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mov 0xfd00e2ed,e2
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mov 0xfd00e3ed,e3
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mov 0xfd00e4ed,e4
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mov 0xfd00e5ed,e5
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mov 0xfd00e6ed,e6
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mov 0xfd00e7ed,e7
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mov 0xfd00d0ed,d0
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mov 0xfd00d1ed,d1
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mov 0xfd00d2ed,d2
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mov 0xfd00d3ed,d3
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mov 0xfd00a0ed,a0
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mov 0xfd00a1ed,a1
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mov 0xfd00a2ed,a2
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# we may be holding current in E2
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#ifdef CONFIG_MN10300_CURRENT_IN_E2
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mov init_task,e2
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#endif
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# initialise the processor and the unit
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call processor_init[],0
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call unit_init[],0
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#ifdef CONFIG_SMP
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# mark the primary CPU in cpu_boot_map
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mov cpu_boot_map,a0
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mov 0x1,d0
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mov d0,(a0)
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# signal each secondary CPU to begin booting
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mov 0x1,d2 # CPU ID
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loop_request_boot_secondary:
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mov d2,a0
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# send SMP_BOOT_IPI to secondary CPU
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asl CROSS_ICR_CPU_SHIFT,a0
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add CROSS_GxICR(SMP_BOOT_IRQ,0),a0
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movhu (a0),d0
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or GxICR_REQUEST|GxICR_DETECT,d0
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movhu d0,(a0)
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movhu (a0),d0 # flush
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# wait up to 100ms for AP's IPI to be received
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clr d3
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wait_on_secondary_boot:
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mov DELAY_TIME_BOOT_IPI,d0
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call __delay[],0
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inc d3
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mov cpu_boot_map,a0
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mov (a0),d0
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lsr d2,d0
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btst 0x1,d0
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bne 1f
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cmp TIME_OUT_COUNT_BOOT_IPI,d3
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bne wait_on_secondary_boot
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1:
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inc d2
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cmp NR_CPUS,d2
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bne loop_request_boot_secondary
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_GDBSTUB
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call gdbstub_init[],0
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#ifdef CONFIG_GDBSTUB_IMMEDIATE
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.globl __gdbstub_pause
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__gdbstub_pause:
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bra __gdbstub_pause
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#endif
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#endif
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jmp start_kernel
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.size _start,.-_start
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###############################################################################
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#
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# Secondary CPU boot point
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#
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###############################################################################
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#ifdef CONFIG_SMP
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startup_secondary:
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# preload the PGD pointer register
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mov swapper_pg_dir,d0
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mov d0,(PTBR)
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clr d0
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movbu d0,(PIDR)
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# turn on the TLBs
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mov MMUCTR_IIV|MMUCTR_DIV,d0
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mov d0,(MMUCTR)
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#ifdef CONFIG_AM34_2
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mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0
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#else
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mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
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#endif
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mov d0,(MMUCTR)
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# turn on AM33v2 exception handling mode and set the trap table base
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movhu (CPUP),d0
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or CPUP_EXM_AM33V2,d0
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movhu d0,(CPUP)
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# set the interrupt vector table
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mov CONFIG_INTERRUPT_VECTOR_BASE,d0
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mov d0,(TBR)
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# invalidate and enable both of the caches
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mov ECHCTR,a0
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clr d0
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mov d0,(a0)
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mov CHCTR,a0
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clr d0
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movhu d0,(a0) # turn off first
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mov CHCTR_ICINV|CHCTR_DCINV,d0
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movhu d0,(a0)
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setlb
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mov (a0),d0
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btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
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lne
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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#ifdef CONFIG_MN10300_CACHE_WBACK
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#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
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#else
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0
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#endif /* !NOWRALLOC */
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#else
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
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#endif /* WBACK */
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movhu d0,(a0) # enable
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#endif /* ENABLED */
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# Clear the boot IPI interrupt for this CPU
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movhu (GxICR(SMP_BOOT_IRQ)),d0
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and ~GxICR_REQUEST,d0
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movhu d0,(GxICR(SMP_BOOT_IRQ))
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movhu (GxICR(SMP_BOOT_IRQ)),d0 # flush
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/* get stack */
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mov CONFIG_INTERRUPT_VECTOR_BASE + CONFIG_BOOT_STACK_OFFSET,a0
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mov (CPUID),d0
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and CPUID_MASK,d0
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mulu CONFIG_BOOT_STACK_SIZE,d0
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sub d0,a0
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mov a0,sp
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# init interrupt for AP
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call smp_prepare_cpu_init[],0
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# mark this secondary CPU in cpu_boot_map
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mov (CPUID),d0
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mov 0x1,d1
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asl d0,d1
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mov cpu_boot_map,a0
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bset d1,(a0)
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or EPSW_IE|EPSW_IM_1,epsw # permit level 0 interrupts
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nop
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nop
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#ifdef CONFIG_MN10300_CACHE_WBACK
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# flush the local cache if it's in writeback mode
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call mn10300_local_dcache_flush_inv[],0
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setlb
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mov (CHCTR),d0
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btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
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lne
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#endif
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# now sleep waiting for further instructions
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secondary_sleep:
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mov CPUM_SLEEP,d0
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movhu d0,(CPUM)
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nop
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nop
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bra secondary_sleep
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.size startup_secondary,.-startup_secondary
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#endif /* CONFIG_SMP */
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###############################################################################
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#
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#
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#
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###############################################################################
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ENTRY(__head_end)
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/*
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* This is initialized to disallow all access to the low 2G region
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* - the high 2G region is managed directly by the MMU
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* - range 0x70000000-0x7C000000 are initialised for use by VMALLOC
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*/
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.section .bss
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.balign PAGE_SIZE
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ENTRY(swapper_pg_dir)
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.space PTRS_PER_PGD*4
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/*
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* The page tables are initialized to only 8MB here - the final page
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* tables are set up later depending on memory size.
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*/
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.balign PAGE_SIZE
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ENTRY(empty_zero_page)
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.space PAGE_SIZE
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.balign PAGE_SIZE
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ENTRY(empty_bad_page)
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.space PAGE_SIZE
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.balign PAGE_SIZE
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ENTRY(empty_bad_pte_table)
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.space PAGE_SIZE
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.balign PAGE_SIZE
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ENTRY(large_page_table)
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.space PAGE_SIZE
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.balign PAGE_SIZE
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ENTRY(kernel_vmalloc_ptes)
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.space ((VMALLOC_END-VMALLOC_START)/PAGE_SIZE)*4
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