Stefan Roese f4151b9ba8 [POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG ... Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>		2007-12-23 13:31:16 -06:00
..
4xx_mmu.c	[POWERPC] ppc405 Fix arithmatic rollover bug when memory size under 16M	2007-11-01 07:15:59 -05:00
44x_mmu.c	[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG	2007-12-23 13:31:16 -06:00
Makefile	…
fault.c	[POWERPC] 4xx: Fix 4xx flush_tlb_page()	2007-11-01 07:15:09 -05:00
fsl_booke_mmu.c	…
hashtable.S	…
init.c	[POWERPC] Fix 8xx build breakage due to _tlbie changes	2007-11-20 18:42:00 +11:00
mem_pieces.c	…
mem_pieces.h	…
mmu_context.c	…
mmu_decl.h	[POWERPC] Fix 8xx build breakage due to _tlbie changes	2007-11-20 18:42:00 +11:00
pgtable.c	…
ppc_mmu.c	…
tlb.c	…