261 lines
6.8 KiB
C
261 lines
6.8 KiB
C
/*
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* linux/arch/arm/plat-omap/dmtimer.c
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*
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* OMAP Dual-Mode Timers
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include <asm/arch/dmtimer.h>
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#include <asm/io.h>
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#include <asm/arch/irqs.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#define OMAP_TIMER_COUNT 8
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#define OMAP_TIMER_ID_REG 0x00
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#define OMAP_TIMER_OCP_CFG_REG 0x10
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#define OMAP_TIMER_SYS_STAT_REG 0x14
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#define OMAP_TIMER_STAT_REG 0x18
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#define OMAP_TIMER_INT_EN_REG 0x1c
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#define OMAP_TIMER_WAKEUP_EN_REG 0x20
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#define OMAP_TIMER_CTRL_REG 0x24
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#define OMAP_TIMER_COUNTER_REG 0x28
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#define OMAP_TIMER_LOAD_REG 0x2c
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#define OMAP_TIMER_TRIGGER_REG 0x30
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#define OMAP_TIMER_WRITE_PEND_REG 0x34
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#define OMAP_TIMER_MATCH_REG 0x38
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#define OMAP_TIMER_CAPTURE_REG 0x3c
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#define OMAP_TIMER_IF_CTRL_REG 0x40
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static struct dmtimer_info_struct {
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struct list_head unused_timers;
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struct list_head reserved_timers;
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} dm_timer_info;
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static struct omap_dm_timer dm_timers[] = {
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{ .base=0xfffb1400, .irq=INT_1610_GPTIMER1 },
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{ .base=0xfffb1c00, .irq=INT_1610_GPTIMER2 },
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{ .base=0xfffb2400, .irq=INT_1610_GPTIMER3 },
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{ .base=0xfffb2c00, .irq=INT_1610_GPTIMER4 },
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{ .base=0xfffb3400, .irq=INT_1610_GPTIMER5 },
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{ .base=0xfffb3c00, .irq=INT_1610_GPTIMER6 },
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{ .base=0xfffb4400, .irq=INT_1610_GPTIMER7 },
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{ .base=0xfffb4c00, .irq=INT_1610_GPTIMER8 },
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{ .base=0x0 },
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};
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static spinlock_t dm_timer_lock;
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inline void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
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{
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omap_writel(value, timer->base + reg);
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while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
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;
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}
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u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
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{
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return omap_readl(timer->base + reg);
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}
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int omap_dm_timers_active(void)
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{
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struct omap_dm_timer *timer;
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for (timer = &dm_timers[0]; timer->base; ++timer)
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if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
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OMAP_TIMER_CTRL_ST)
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return 1;
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return 0;
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}
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void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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int n = (timer - dm_timers) << 1;
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u32 l;
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l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
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l |= source << n;
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omap_writel(l, MOD_CONF_CTRL_1);
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}
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static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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/* Reset and set posted mode */
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, 0x02);
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omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_ARMXOR);
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}
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struct omap_dm_timer * omap_dm_timer_request(void)
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{
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struct omap_dm_timer *timer = NULL;
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unsigned long flags;
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spin_lock_irqsave(&dm_timer_lock, flags);
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if (!list_empty(&dm_timer_info.unused_timers)) {
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timer = (struct omap_dm_timer *)
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dm_timer_info.unused_timers.next;
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list_move_tail((struct list_head *)timer,
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&dm_timer_info.reserved_timers);
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}
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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return timer;
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}
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void omap_dm_timer_free(struct omap_dm_timer *timer)
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{
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unsigned long flags;
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omap_dm_timer_reset(timer);
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spin_lock_irqsave(&dm_timer_lock, flags);
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list_move_tail((struct list_head *)timer, &dm_timer_info.unused_timers);
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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}
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void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
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unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
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}
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unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
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{
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return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
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}
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void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
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}
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void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l |= OMAP_TIMER_CTRL_AR;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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void omap_dm_timer_trigger(struct omap_dm_timer *timer)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 1);
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}
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void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l |= value & 0x3;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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void omap_dm_timer_start(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l |= OMAP_TIMER_CTRL_ST;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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void omap_dm_timer_stop(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l &= ~0x1;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
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{
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return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
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}
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void omap_dm_timer_reset_counter(struct omap_dm_timer *timer)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 0);
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}
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void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
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}
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void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
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}
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void omap_dm_timer_enable_compare(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l |= OMAP_TIMER_CTRL_CE;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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static inline void __dm_timer_init(void)
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{
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struct omap_dm_timer *timer;
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spin_lock_init(&dm_timer_lock);
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INIT_LIST_HEAD(&dm_timer_info.unused_timers);
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INIT_LIST_HEAD(&dm_timer_info.reserved_timers);
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timer = &dm_timers[0];
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while (timer->base) {
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list_add_tail((struct list_head *)timer, &dm_timer_info.unused_timers);
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omap_dm_timer_reset(timer);
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timer++;
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}
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}
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static int __init omap_dm_timer_init(void)
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{
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if (cpu_is_omap16xx())
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__dm_timer_init();
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return 0;
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}
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arch_initcall(omap_dm_timer_init);
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