673 lines
18 KiB
C
673 lines
18 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/tioca_provider.h>
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uint32_t tioca_gart_found;
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EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */
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LIST_HEAD(tioca_list);
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EXPORT_SYMBOL(tioca_list); /* used by agp-sgi */
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static int tioca_gart_init(struct tioca_kernel *);
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/**
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* tioca_gart_init - Initialize SGI TIOCA GART
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* @tioca_common: ptr to common prom/kernel struct identifying the
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*
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* If the indicated tioca has devices present, initialize its associated
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* GART MMR's and kernel memory.
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*/
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static int
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tioca_gart_init(struct tioca_kernel *tioca_kern)
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{
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uint64_t ap_reg;
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uint64_t offset;
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struct page *tmp;
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struct tioca_common *tioca_common;
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volatile struct tioca *ca_base;
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tioca_common = tioca_kern->ca_common;
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ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
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if (list_empty(tioca_kern->ca_devices))
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return 0;
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ap_reg = 0;
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/*
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* Validate aperature size
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*/
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switch (CA_APERATURE_SIZE >> 20) {
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case 4:
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ap_reg |= (0x3ff << CA_GART_AP_SIZE_SHFT); /* 4MB */
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break;
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case 8:
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ap_reg |= (0x3fe << CA_GART_AP_SIZE_SHFT); /* 8MB */
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break;
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case 16:
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ap_reg |= (0x3fc << CA_GART_AP_SIZE_SHFT); /* 16MB */
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break;
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case 32:
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ap_reg |= (0x3f8 << CA_GART_AP_SIZE_SHFT); /* 32 MB */
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break;
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case 64:
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ap_reg |= (0x3f0 << CA_GART_AP_SIZE_SHFT); /* 64 MB */
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break;
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case 128:
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ap_reg |= (0x3e0 << CA_GART_AP_SIZE_SHFT); /* 128 MB */
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break;
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case 256:
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ap_reg |= (0x3c0 << CA_GART_AP_SIZE_SHFT); /* 256 MB */
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break;
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case 512:
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ap_reg |= (0x380 << CA_GART_AP_SIZE_SHFT); /* 512 MB */
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break;
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case 1024:
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ap_reg |= (0x300 << CA_GART_AP_SIZE_SHFT); /* 1GB */
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break;
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case 2048:
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ap_reg |= (0x200 << CA_GART_AP_SIZE_SHFT); /* 2GB */
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break;
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case 4096:
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ap_reg |= (0x000 << CA_GART_AP_SIZE_SHFT); /* 4 GB */
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break;
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default:
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printk(KERN_ERR "%s: Invalid CA_APERATURE_SIZE "
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"0x%lx\n", __FUNCTION__, (ulong) CA_APERATURE_SIZE);
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return -1;
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}
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/*
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* Set up other aperature parameters
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*/
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if (PAGE_SIZE >= 16384) {
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tioca_kern->ca_ap_pagesize = 16384;
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ap_reg |= CA_GART_PAGE_SIZE;
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} else {
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tioca_kern->ca_ap_pagesize = 4096;
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}
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tioca_kern->ca_ap_size = CA_APERATURE_SIZE;
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tioca_kern->ca_ap_bus_base = CA_APERATURE_BASE;
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tioca_kern->ca_gart_entries =
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tioca_kern->ca_ap_size / tioca_kern->ca_ap_pagesize;
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ap_reg |= (CA_GART_AP_ENB_AGP | CA_GART_AP_ENB_PCI);
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ap_reg |= tioca_kern->ca_ap_bus_base;
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/*
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* Allocate and set up the GART
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*/
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tioca_kern->ca_gart_size = tioca_kern->ca_gart_entries * sizeof(u64);
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tmp =
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alloc_pages_node(tioca_kern->ca_closest_node,
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GFP_KERNEL | __GFP_ZERO,
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get_order(tioca_kern->ca_gart_size));
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if (!tmp) {
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printk(KERN_ERR "%s: Could not allocate "
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"%lu bytes (order %d) for GART\n",
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__FUNCTION__,
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tioca_kern->ca_gart_size,
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get_order(tioca_kern->ca_gart_size));
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return -ENOMEM;
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}
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tioca_kern->ca_gart = page_address(tmp);
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tioca_kern->ca_gart_coretalk_addr =
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PHYS_TO_TIODMA(virt_to_phys(tioca_kern->ca_gart));
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/*
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* Compute PCI/AGP convenience fields
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*/
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offset = CA_PCI32_MAPPED_BASE - CA_APERATURE_BASE;
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tioca_kern->ca_pciap_base = CA_PCI32_MAPPED_BASE;
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tioca_kern->ca_pciap_size = CA_PCI32_MAPPED_SIZE;
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tioca_kern->ca_pcigart_start = offset / tioca_kern->ca_ap_pagesize;
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tioca_kern->ca_pcigart_base =
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tioca_kern->ca_gart_coretalk_addr + offset;
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tioca_kern->ca_pcigart =
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&tioca_kern->ca_gart[tioca_kern->ca_pcigart_start];
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tioca_kern->ca_pcigart_entries =
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tioca_kern->ca_pciap_size / tioca_kern->ca_ap_pagesize;
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tioca_kern->ca_pcigart_pagemap =
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kzalloc(tioca_kern->ca_pcigart_entries / 8, GFP_KERNEL);
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if (!tioca_kern->ca_pcigart_pagemap) {
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free_pages((unsigned long)tioca_kern->ca_gart,
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get_order(tioca_kern->ca_gart_size));
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return -1;
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}
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offset = CA_AGP_MAPPED_BASE - CA_APERATURE_BASE;
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tioca_kern->ca_gfxap_base = CA_AGP_MAPPED_BASE;
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tioca_kern->ca_gfxap_size = CA_AGP_MAPPED_SIZE;
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tioca_kern->ca_gfxgart_start = offset / tioca_kern->ca_ap_pagesize;
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tioca_kern->ca_gfxgart_base =
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tioca_kern->ca_gart_coretalk_addr + offset;
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tioca_kern->ca_gfxgart =
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&tioca_kern->ca_gart[tioca_kern->ca_gfxgart_start];
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tioca_kern->ca_gfxgart_entries =
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tioca_kern->ca_gfxap_size / tioca_kern->ca_ap_pagesize;
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/*
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* various control settings:
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* use agp op-combining
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* use GET semantics to fetch memory
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* participate in coherency domain
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* DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
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*/
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ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY; /* PV895469 ? */
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ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
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ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
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tioca_kern->ca_gart_iscoherent = 1;
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ca_base->ca_control2 &=
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~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
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/*
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* Unmask GART fetch error interrupts. Clear residual errors first.
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*/
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ca_base->ca_int_status_alias = CA_GART_FETCH_ERR;
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ca_base->ca_mult_error_alias = CA_GART_FETCH_ERR;
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ca_base->ca_int_mask &= ~CA_GART_FETCH_ERR;
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/*
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* Program the aperature and gart registers in TIOCA
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*/
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ca_base->ca_gart_aperature = ap_reg;
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ca_base->ca_gart_ptr_table = tioca_kern->ca_gart_coretalk_addr | 1;
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return 0;
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}
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/**
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* tioca_fastwrite_enable - enable AGP FW for a tioca and its functions
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* @tioca_kernel: structure representing the CA
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*
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* Given a CA, scan all attached functions making sure they all support
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* FastWrite. If so, enable FastWrite for all functions and the CA itself.
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*/
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void
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tioca_fastwrite_enable(struct tioca_kernel *tioca_kern)
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{
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int cap_ptr;
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uint64_t ca_control1;
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uint32_t reg;
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struct tioca *tioca_base;
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struct pci_dev *pdev;
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struct tioca_common *common;
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common = tioca_kern->ca_common;
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/*
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* Scan all vga controllers on this bus making sure they all
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* suport FW. If not, return.
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*/
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list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
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if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
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continue;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return; /* no AGP CAP means no FW */
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pci_read_config_dword(pdev, cap_ptr + PCI_AGP_STATUS, ®);
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if (!(reg & PCI_AGP_STATUS_FW))
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return; /* function doesn't support FW */
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}
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/*
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* Set fw for all vga fn's
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*/
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list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
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if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
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continue;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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pci_read_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, ®);
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reg |= PCI_AGP_COMMAND_FW;
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pci_write_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, reg);
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}
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/*
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* Set ca's fw to match
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*/
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tioca_base = (struct tioca *)common->ca_common.bs_base;
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ca_control1 = tioca_base->ca_control1;
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ca_control1 |= CA_AGP_FW_ENABLE;
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tioca_base->ca_control1 = ca_control1;
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}
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EXPORT_SYMBOL(tioca_fastwrite_enable); /* used by agp-sgi */
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/**
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* tioca_dma_d64 - create a DMA mapping using 64-bit direct mode
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* @paddr: system physical address
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*
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* Map @paddr into 64-bit CA bus space. No device context is necessary.
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* Bits 53:0 come from the coretalk address. We just need to mask in the
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* following optional bits of the 64-bit pci address:
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*
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* 63:60 - Coretalk Packet Type - 0x1 for Mem Get/Put (coherent)
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* 0x2 for PIO (non-coherent)
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* We will always use 0x1
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* 55:55 - Swap bytes Currently unused
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*/
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static uint64_t
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tioca_dma_d64(unsigned long paddr)
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{
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dma_addr_t bus_addr;
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bus_addr = PHYS_TO_TIODMA(paddr);
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BUG_ON(!bus_addr);
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BUG_ON(bus_addr >> 54);
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/* Set upper nibble to Cache Coherent Memory op */
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bus_addr |= (1UL << 60);
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return bus_addr;
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}
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/**
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* tioca_dma_d48 - create a DMA mapping using 48-bit direct mode
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* @pdev: linux pci_dev representing the function
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* @paddr: system physical address
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*
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* Map @paddr into 64-bit bus space of the CA associated with @pcidev_info.
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*
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* The CA agp 48 bit direct address falls out as follows:
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*
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* When direct mapping AGP addresses, the 48 bit AGP address is
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* constructed as follows:
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*
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* [47:40] - Low 8 bits of the page Node ID extracted from coretalk
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* address [47:40]. The upper 8 node bits are fixed
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* and come from the xxx register bits [5:0]
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* [39:38] - Chiplet ID extracted from coretalk address [39:38]
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* [37:00] - node offset extracted from coretalk address [37:00]
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*
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* Since the node id in general will be non-zero, and the chiplet id
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* will always be non-zero, it follows that the device must support
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* a dma mask of at least 0xffffffffff (40 bits) to target node 0
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* and in general should be 0xffffffffffff (48 bits) to target nodes
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* up to 255. Nodes above 255 need the support of the xxx register,
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* and so a given CA can only directly target nodes in the range
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* xxx - xxx+255.
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*/
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static uint64_t
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tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
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{
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struct tioca_common *tioca_common;
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struct tioca *ca_base;
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uint64_t ct_addr;
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dma_addr_t bus_addr;
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uint32_t node_upper;
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uint64_t agp_dma_extn;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
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tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
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ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
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ct_addr = PHYS_TO_TIODMA(paddr);
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if (!ct_addr)
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return 0;
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bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
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node_upper = ct_addr >> 48;
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if (node_upper > 64) {
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printk(KERN_ERR "%s: coretalk addr 0x%p node id out "
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"of range\n", __FUNCTION__, (void *)ct_addr);
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return 0;
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}
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agp_dma_extn = ca_base->ca_agp_dma_addr_extn;
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if (node_upper != (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT)) {
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printk(KERN_ERR "%s: coretalk upper node (%u) "
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"mismatch with ca_agp_dma_addr_extn (%lu)\n",
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__FUNCTION__,
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node_upper, (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT));
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return 0;
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}
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return bus_addr;
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}
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/**
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* tioca_dma_mapped - create a DMA mapping using a CA GART
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* @pdev: linux pci_dev representing the function
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* @paddr: host physical address to map
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* @req_size: len (bytes) to map
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*
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* Map @paddr into CA address space using the GART mechanism. The mapped
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* dma_addr_t is guarenteed to be contiguous in CA bus space.
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*/
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static dma_addr_t
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tioca_dma_mapped(struct pci_dev *pdev, uint64_t paddr, size_t req_size)
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{
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int i, ps, ps_shift, entry, entries, mapsize, last_entry;
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uint64_t xio_addr, end_xio_addr;
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struct tioca_common *tioca_common;
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struct tioca_kernel *tioca_kern;
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dma_addr_t bus_addr = 0;
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struct tioca_dmamap *ca_dmamap;
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void *map;
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unsigned long flags;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);;
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tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
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tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
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xio_addr = PHYS_TO_TIODMA(paddr);
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if (!xio_addr)
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return 0;
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spin_lock_irqsave(&tioca_kern->ca_lock, flags);
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/*
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* allocate a map struct
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*/
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ca_dmamap = kzalloc(sizeof(struct tioca_dmamap), GFP_ATOMIC);
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if (!ca_dmamap)
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goto map_return;
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/*
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* Locate free entries that can hold req_size. Account for
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* unaligned start/length when allocating.
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*/
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ps = tioca_kern->ca_ap_pagesize; /* will be power of 2 */
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ps_shift = ffs(ps) - 1;
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end_xio_addr = xio_addr + req_size - 1;
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entries = (end_xio_addr >> ps_shift) - (xio_addr >> ps_shift) + 1;
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map = tioca_kern->ca_pcigart_pagemap;
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mapsize = tioca_kern->ca_pcigart_entries;
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entry = find_first_zero_bit(map, mapsize);
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while (entry < mapsize) {
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last_entry = find_next_bit(map, mapsize, entry);
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if (last_entry - entry >= entries)
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break;
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entry = find_next_zero_bit(map, mapsize, last_entry);
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}
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if (entry > mapsize)
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goto map_return;
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for (i = 0; i < entries; i++)
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set_bit(entry + i, map);
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bus_addr = tioca_kern->ca_pciap_base + (entry * ps);
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ca_dmamap->cad_dma_addr = bus_addr;
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ca_dmamap->cad_gart_size = entries;
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ca_dmamap->cad_gart_entry = entry;
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list_add(&ca_dmamap->cad_list, &tioca_kern->ca_dmamaps);
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if (xio_addr % ps) {
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tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
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bus_addr += xio_addr & (ps - 1);
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xio_addr &= ~(ps - 1);
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xio_addr += ps;
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entry++;
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}
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while (xio_addr < end_xio_addr) {
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tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
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xio_addr += ps;
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entry++;
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}
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tioca_tlbflush(tioca_kern);
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map_return:
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spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
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return bus_addr;
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}
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/**
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* tioca_dma_unmap - release CA mapping resources
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* @pdev: linux pci_dev representing the function
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* @bus_addr: bus address returned by an earlier tioca_dma_map
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* @dir: mapping direction (unused)
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*
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* Locate mapping resources associated with @bus_addr and release them.
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* For mappings created using the direct modes (64 or 48) there are no
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* resources to release.
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*/
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static void
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tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
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{
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int i, entry;
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struct tioca_common *tioca_common;
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struct tioca_kernel *tioca_kern;
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struct tioca_dmamap *map;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
|
|
unsigned long flags;
|
|
|
|
tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
|
|
tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
|
|
|
|
/* return straight away if this isn't be a mapped address */
|
|
|
|
if (bus_addr < tioca_kern->ca_pciap_base ||
|
|
bus_addr >= (tioca_kern->ca_pciap_base + tioca_kern->ca_pciap_size))
|
|
return;
|
|
|
|
spin_lock_irqsave(&tioca_kern->ca_lock, flags);
|
|
|
|
list_for_each_entry(map, &tioca_kern->ca_dmamaps, cad_list)
|
|
if (map->cad_dma_addr == bus_addr)
|
|
break;
|
|
|
|
BUG_ON(map == NULL);
|
|
|
|
entry = map->cad_gart_entry;
|
|
|
|
for (i = 0; i < map->cad_gart_size; i++, entry++) {
|
|
clear_bit(entry, tioca_kern->ca_pcigart_pagemap);
|
|
tioca_kern->ca_pcigart[entry] = 0;
|
|
}
|
|
tioca_tlbflush(tioca_kern);
|
|
|
|
list_del(&map->cad_list);
|
|
spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
|
|
kfree(map);
|
|
}
|
|
|
|
/**
|
|
* tioca_dma_map - map pages for PCI DMA
|
|
* @pdev: linux pci_dev representing the function
|
|
* @paddr: host physical address to map
|
|
* @byte_count: bytes to map
|
|
*
|
|
* This is the main wrapper for mapping host physical pages to CA PCI space.
|
|
* The mapping mode used is based on the devices dma_mask. As a last resort
|
|
* use the GART mapped mode.
|
|
*/
|
|
static uint64_t
|
|
tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
|
|
{
|
|
uint64_t mapaddr;
|
|
|
|
/*
|
|
* If card is 64 or 48 bit addresable, use a direct mapping. 32
|
|
* bit direct is so restrictive w.r.t. where the memory resides that
|
|
* we don't use it even though CA has some support.
|
|
*/
|
|
|
|
if (pdev->dma_mask == ~0UL)
|
|
mapaddr = tioca_dma_d64(paddr);
|
|
else if (pdev->dma_mask == 0xffffffffffffUL)
|
|
mapaddr = tioca_dma_d48(pdev, paddr);
|
|
else
|
|
mapaddr = 0;
|
|
|
|
/* Last resort ... use PCI portion of CA GART */
|
|
|
|
if (mapaddr == 0)
|
|
mapaddr = tioca_dma_mapped(pdev, paddr, byte_count);
|
|
|
|
return mapaddr;
|
|
}
|
|
|
|
/**
|
|
* tioca_error_intr_handler - SGI TIO CA error interrupt handler
|
|
* @irq: unused
|
|
* @arg: pointer to tioca_common struct for the given CA
|
|
* @pt: unused
|
|
*
|
|
* Handle a CA error interrupt. Simply a wrapper around a SAL call which
|
|
* defers processing to the SGI prom.
|
|
*/
|
|
static irqreturn_t
|
|
tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
|
|
{
|
|
struct tioca_common *soft = arg;
|
|
struct ia64_sal_retval ret_stuff;
|
|
uint64_t segment;
|
|
uint64_t busnum;
|
|
ret_stuff.status = 0;
|
|
ret_stuff.v0 = 0;
|
|
|
|
segment = soft->ca_common.bs_persist_segment;
|
|
busnum = soft->ca_common.bs_persist_busnum;
|
|
|
|
SAL_CALL_NOLOCK(ret_stuff,
|
|
(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
|
|
segment, busnum, 0, 0, 0, 0, 0);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* tioca_bus_fixup - perform final PCI fixup for a TIO CA bus
|
|
* @prom_bussoft: Common prom/kernel struct representing the bus
|
|
*
|
|
* Replicates the tioca_common pointed to by @prom_bussoft in kernel
|
|
* space. Allocates and initializes a kernel-only area for a given CA,
|
|
* and sets up an irq for handling CA error interrupts.
|
|
*
|
|
* On successful setup, returns the kernel version of tioca_common back to
|
|
* the caller.
|
|
*/
|
|
static void *
|
|
tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
|
|
{
|
|
struct tioca_common *tioca_common;
|
|
struct tioca_kernel *tioca_kern;
|
|
struct pci_bus *bus;
|
|
|
|
/* sanity check prom rev */
|
|
|
|
if (sn_sal_rev() < 0x0406) {
|
|
printk
|
|
(KERN_ERR "%s: SGI prom rev 4.06 or greater required "
|
|
"for tioca support\n", __FUNCTION__);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Allocate kernel bus soft and copy from prom.
|
|
*/
|
|
|
|
tioca_common = kzalloc(sizeof(struct tioca_common), GFP_KERNEL);
|
|
if (!tioca_common)
|
|
return NULL;
|
|
|
|
memcpy(tioca_common, prom_bussoft, sizeof(struct tioca_common));
|
|
tioca_common->ca_common.bs_base |= __IA64_UNCACHED_OFFSET;
|
|
|
|
/* init kernel-private area */
|
|
|
|
tioca_kern = kzalloc(sizeof(struct tioca_kernel), GFP_KERNEL);
|
|
if (!tioca_kern) {
|
|
kfree(tioca_common);
|
|
return NULL;
|
|
}
|
|
|
|
tioca_kern->ca_common = tioca_common;
|
|
spin_lock_init(&tioca_kern->ca_lock);
|
|
INIT_LIST_HEAD(&tioca_kern->ca_dmamaps);
|
|
tioca_kern->ca_closest_node =
|
|
nasid_to_cnodeid(tioca_common->ca_closest_nasid);
|
|
tioca_common->ca_kernel_private = (uint64_t) tioca_kern;
|
|
|
|
bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
|
|
tioca_common->ca_common.bs_persist_busnum);
|
|
BUG_ON(!bus);
|
|
tioca_kern->ca_devices = &bus->devices;
|
|
|
|
/* init GART */
|
|
|
|
if (tioca_gart_init(tioca_kern) < 0) {
|
|
kfree(tioca_kern);
|
|
kfree(tioca_common);
|
|
return NULL;
|
|
}
|
|
|
|
tioca_gart_found++;
|
|
list_add(&tioca_kern->ca_list, &tioca_list);
|
|
|
|
if (request_irq(SGI_TIOCA_ERROR,
|
|
tioca_error_intr_handler,
|
|
SA_SHIRQ, "TIOCA error", (void *)tioca_common))
|
|
printk(KERN_WARNING
|
|
"%s: Unable to get irq %d. "
|
|
"Error interrupts won't be routed for TIOCA bus %d\n",
|
|
__FUNCTION__, SGI_TIOCA_ERROR,
|
|
(int)tioca_common->ca_common.bs_persist_busnum);
|
|
|
|
/* Setup locality information */
|
|
controller->node = tioca_kern->ca_closest_node;
|
|
return tioca_common;
|
|
}
|
|
|
|
static struct sn_pcibus_provider tioca_pci_interfaces = {
|
|
.dma_map = tioca_dma_map,
|
|
.dma_map_consistent = tioca_dma_map,
|
|
.dma_unmap = tioca_dma_unmap,
|
|
.bus_fixup = tioca_bus_fixup,
|
|
.force_interrupt = NULL,
|
|
.target_interrupt = NULL
|
|
};
|
|
|
|
/**
|
|
* tioca_init_provider - init SN PCI provider ops for TIO CA
|
|
*/
|
|
int
|
|
tioca_init_provider(void)
|
|
{
|
|
sn_pci_provider[PCIIO_ASIC_TYPE_TIOCA] = &tioca_pci_interfaces;
|
|
return 0;
|
|
}
|