64 lines
2.4 KiB
C
64 lines
2.4 KiB
C
/*
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* stmp37xx: GPMI register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
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#define REGS_GPMI_PHYS 0x8000C000
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#define REGS_GPMI_SIZE 0x2000
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#define HW_GPMI_CTRL0 0x0
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#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
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#define BP_GPMI_CTRL0_XFER_COUNT 0
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#define BM_GPMI_CTRL0_CS 0x00300000
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#define BP_GPMI_CTRL0_CS 20
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#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
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#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
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#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
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#define BP_GPMI_CTRL0_COMMAND_MODE 24
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#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
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#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
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#define BM_GPMI_CTRL0_RUN 0x20000000
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#define BM_GPMI_CTRL0_CLKGATE 0x40000000
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#define BM_GPMI_CTRL0_SFTRST 0x80000000
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#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
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#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
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#define BP_GPMI_ECCCTRL_ECC_CMD 13
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#define HW_GPMI_CTRL1 0x60
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#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
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#define BP_GPMI_CTRL1_GPMI_MODE 0
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#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
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#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
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#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
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#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
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#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
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#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
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#define HW_GPMI_TIMING0 0x70
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#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
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#define BP_GPMI_TIMING0_DATA_SETUP 0
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#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
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#define BP_GPMI_TIMING0_DATA_HOLD 8
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#define HW_GPMI_TIMING1 0x80
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#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
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#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
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