b3c6b76ffb
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL bit. MPU PLL is driven by 512*CLK32 for each case. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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.. | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
cpufreq.c | ||
dma.c | ||
generic.c | ||
generic.h | ||
irq.c | ||
leds-mx1ads.c | ||
leds.c | ||
leds.h | ||
mx1ads.c | ||
time.c |