Changhwan Youn a50eb1c768 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register ... This patch is applied according to the commit 1a8e41cd67 (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register). Actually, S5PV310 has same cache controller(PL310). Following is from Catalin Marinas' commit. Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Cc: <stable@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>		2010-12-30 09:37:02 +09:00
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arm	ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register	2010-12-30 09:37:02 +09:00
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ia64	…
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mips	MIPS: Fix build errors in sc-mips.c	2010-12-17 19:44:35 +00:00
mn10300	clarify a usage constraint for cnt32_to_63()	2010-12-20 09:07:35 -08:00
parisc	parisc: convert the rest of the irq handlers to simple/percpu	2010-12-04 11:15:19 -05:00
powerpc	powerpc/mpc5200: include fs.h in mpc52xx_gpt.c	2010-12-23 12:08:02 -07:00
s390	…
score	…
sh	sh: Fix up SH7201 clkfwk build.	2010-12-24 12:15:57 +09:00
sparc	Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6	2010-12-14 17:34:00 -08:00
tile	arch/tile: handle rt_sigreturn() more cleanly	2010-12-17 16:59:29 -05:00
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x86	x86/microcode: Fix double vfree() and remove redundant pointer checks before vfree()	2010-12-27 14:33:30 +01:00
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