119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
/*
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* arch/ppc/platforms/4xx/ibm405gpr.c
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*
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* Author: Armin Kuster <akuster@mvista.com>
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*
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* 2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <platforms/4xx/ibm405gpr.h>
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#include <asm/ibm4xx.h>
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#include <asm/ocp.h>
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#include <asm/ppc4xx_pic.h>
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static struct ocp_func_emac_data ibm405gpr_emac0_def = {
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.rgmii_idx = -1, /* No RGMII */
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.rgmii_mux = -1, /* No RGMII */
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.zmii_idx = -1, /* ZMII device index */
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.zmii_mux = 0, /* ZMII input of this EMAC */
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.mal_idx = 0, /* MAL device index */
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.mal_rx_chan = 0, /* MAL rx channel number */
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.mal_tx_chan = 0, /* MAL tx channel number */
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.wol_irq = 9, /* WOL interrupt number */
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.mdio_idx = -1, /* No shared MDIO */
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.tah_idx = -1, /* No TAH */
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};
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OCP_SYSFS_EMAC_DATA()
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static struct ocp_func_mal_data ibm405gpr_mal0_def = {
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.num_tx_chans = 1, /* Number of TX channels */
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.num_rx_chans = 1, /* Number of RX channels */
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.txeob_irq = 11, /* TX End Of Buffer IRQ */
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.rxeob_irq = 12, /* RX End Of Buffer IRQ */
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.txde_irq = 13, /* TX Descriptor Error IRQ */
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.rxde_irq = 14, /* RX Descriptor Error IRQ */
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.serr_irq = 10, /* MAL System Error IRQ */
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.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
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};
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OCP_SYSFS_MAL_DATA()
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static struct ocp_func_iic_data ibm405gpr_iic0_def = {
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.fast_mode = 0, /* Use standad mode (100Khz) */
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};
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OCP_SYSFS_IIC_DATA()
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struct ocp_def core_ocp[] = {
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_OPB,
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.index = 0,
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.paddr = 0xEF600000,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_16550,
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.index = 0,
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.paddr = UART0_IO_BASE,
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.irq = UART0_INT,
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.pm = IBM_CPM_UART0
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_16550,
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.index = 1,
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.paddr = UART1_IO_BASE,
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.irq = UART1_INT,
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.pm = IBM_CPM_UART1
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_IIC,
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.paddr = 0xEF600500,
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.irq = 2,
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.pm = IBM_CPM_IIC0,
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.additions = &ibm405gpr_iic0_def,
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.show = &ocp_show_iic_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_GPIO,
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.paddr = 0xEF600700,
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.irq = OCP_IRQ_NA,
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.pm = IBM_CPM_GPIO0
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_MAL,
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.paddr = OCP_PADDR_NA,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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.additions = &ibm405gpr_mal0_def,
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.show = &ocp_show_mal_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_EMAC,
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.index = 0,
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.paddr = EMAC0_BASE,
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.irq = 15,
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.pm = IBM_CPM_EMAC0,
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.additions = &ibm405gpr_emac0_def,
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.show = &ocp_show_emac_data,
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},
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{ .vendor = OCP_VENDOR_INVALID
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}
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};
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/* Polarity and triggering settings for internal interrupt sources */
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struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
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{ .polarity = 0xffffe000,
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.triggering = 0x10000000,
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.ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
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}
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};
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