147 lines
4.1 KiB
C
147 lines
4.1 KiB
C
/*
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* arch/ppc/boot/include/mpsc_defs.h
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*
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* Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
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* Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef _PPC_BOOT_MPSC_DEFS_H__
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#define _PPC_BOOT_MPSC_DEFS_H__
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#define MPSC_NUM_CTLRS 2
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/*
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*****************************************************************************
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*
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* Multi-Protocol Serial Controller Interface Registers
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*
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*****************************************************************************
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*/
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/* Main Configuratino Register Offsets */
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#define MPSC_MMCRL 0x0000
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#define MPSC_MMCRH 0x0004
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#define MPSC_MPCR 0x0008
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#define MPSC_CHR_1 0x000c
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#define MPSC_CHR_2 0x0010
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#define MPSC_CHR_3 0x0014
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#define MPSC_CHR_4 0x0018
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#define MPSC_CHR_5 0x001c
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#define MPSC_CHR_6 0x0020
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#define MPSC_CHR_7 0x0024
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#define MPSC_CHR_8 0x0028
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#define MPSC_CHR_9 0x002c
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#define MPSC_CHR_10 0x0030
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#define MPSC_CHR_11 0x0034
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#define MPSC_MPCR_CL_5 0
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#define MPSC_MPCR_CL_6 1
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#define MPSC_MPCR_CL_7 2
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#define MPSC_MPCR_CL_8 3
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#define MPSC_MPCR_SBL_1 0
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#define MPSC_MPCR_SBL_2 3
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#define MPSC_CHR_2_TEV (1<<1)
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#define MPSC_CHR_2_TA (1<<7)
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#define MPSC_CHR_2_TTCS (1<<9)
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#define MPSC_CHR_2_REV (1<<17)
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#define MPSC_CHR_2_RA (1<<23)
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#define MPSC_CHR_2_CRD (1<<25)
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#define MPSC_CHR_2_EH (1<<31)
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#define MPSC_CHR_2_PAR_ODD 0
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#define MPSC_CHR_2_PAR_SPACE 1
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#define MPSC_CHR_2_PAR_EVEN 2
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#define MPSC_CHR_2_PAR_MARK 3
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/* MPSC Signal Routing */
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#define MPSC_MRR 0x0000
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#define MPSC_RCRR 0x0004
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#define MPSC_TCRR 0x0008
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/*
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*****************************************************************************
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*
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* Serial DMA Controller Interface Registers
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*
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*****************************************************************************
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*/
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#define SDMA_SDC 0x0000
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#define SDMA_SDCM 0x0008
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#define SDMA_RX_DESC 0x0800
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#define SDMA_RX_BUF_PTR 0x0808
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#define SDMA_SCRDP 0x0810
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#define SDMA_TX_DESC 0x0c00
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#define SDMA_SCTDP 0x0c10
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#define SDMA_SFTDP 0x0c14
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#define SDMA_DESC_CMDSTAT_PE (1<<0)
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#define SDMA_DESC_CMDSTAT_CDL (1<<1)
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#define SDMA_DESC_CMDSTAT_FR (1<<3)
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#define SDMA_DESC_CMDSTAT_OR (1<<6)
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#define SDMA_DESC_CMDSTAT_BR (1<<9)
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#define SDMA_DESC_CMDSTAT_MI (1<<10)
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#define SDMA_DESC_CMDSTAT_A (1<<11)
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#define SDMA_DESC_CMDSTAT_AM (1<<12)
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#define SDMA_DESC_CMDSTAT_CT (1<<13)
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#define SDMA_DESC_CMDSTAT_C (1<<14)
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#define SDMA_DESC_CMDSTAT_ES (1<<15)
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#define SDMA_DESC_CMDSTAT_L (1<<16)
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#define SDMA_DESC_CMDSTAT_F (1<<17)
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#define SDMA_DESC_CMDSTAT_P (1<<18)
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#define SDMA_DESC_CMDSTAT_EI (1<<23)
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#define SDMA_DESC_CMDSTAT_O (1<<31)
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#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
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SDMA_DESC_CMDSTAT_EI)
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#define SDMA_SDC_RFT (1<<0)
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#define SDMA_SDC_SFM (1<<1)
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#define SDMA_SDC_BLMR (1<<6)
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#define SDMA_SDC_BLMT (1<<7)
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#define SDMA_SDC_POVR (1<<8)
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#define SDMA_SDC_RIFB (1<<9)
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#define SDMA_SDCM_ERD (1<<7)
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#define SDMA_SDCM_AR (1<<15)
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#define SDMA_SDCM_STD (1<<16)
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#define SDMA_SDCM_TXD (1<<23)
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#define SDMA_SDCM_AT (1<<31)
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#define SDMA_0_CAUSE_RXBUF (1<<0)
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#define SDMA_0_CAUSE_RXERR (1<<1)
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#define SDMA_0_CAUSE_TXBUF (1<<2)
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#define SDMA_0_CAUSE_TXEND (1<<3)
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#define SDMA_1_CAUSE_RXBUF (1<<8)
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#define SDMA_1_CAUSE_RXERR (1<<9)
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#define SDMA_1_CAUSE_TXBUF (1<<10)
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#define SDMA_1_CAUSE_TXEND (1<<11)
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#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
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SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
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#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
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SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
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/* SDMA Interrupt registers */
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#define SDMA_INTR_CAUSE 0x0000
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#define SDMA_INTR_MASK 0x0080
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/*
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*****************************************************************************
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*
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* Baud Rate Generator Interface Registers
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*
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*****************************************************************************
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*/
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#define BRG_BCR 0x0000
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#define BRG_BTR 0x0004
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#endif /*_PPC_BOOT_MPSC_DEFS_H__ */
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