413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001-2005 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/geo.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pic.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/tiocp.h>
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#include "tio.h"
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#include "xtalk/xwidgetdev.h"
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#include "xtalk/hubdev.h"
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extern int sn_ioif_inited;
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/* =====================================================================
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* DMA MANAGEMENT
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*
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* The Bridge ASIC provides three methods of doing DMA: via a "direct map"
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* register available in 32-bit PCI space (which selects a contiguous 2G
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* address space on some other widget), via "direct" addressing via 64-bit
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* PCI space (all destination information comes from the PCI address,
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* including transfer attributes), and via a "mapped" region that allows
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* a bunch of different small mappings to be established with the PMU.
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*
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* For efficiency, we most prefer to use the 32bit direct mapping facility,
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* since it requires no resource allocations. The advantage of using the
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* PMU over the 64-bit direct is that single-cycle PCI addressing can be
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* used; the advantage of using 64-bit direct over PMU addressing is that
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* we do not have to allocate entries in the PMU.
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*/
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static dma_addr_t
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pcibr_dmamap_ate32(struct pcidev_info *info,
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u64 paddr, size_t req_size, u64 flags, int dma_flags)
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{
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struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
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struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
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pdi_pcibus_info;
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u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
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pdi_linux_pcidev->devfn)) - 1;
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int ate_count;
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int ate_index;
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u64 ate_flags = flags | PCI32_ATE_V;
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u64 ate;
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u64 pci_addr;
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u64 xio_addr;
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u64 offset;
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/* PIC in PCI-X mode does not supports 32bit PageMap mode */
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if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
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return 0;
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}
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/* Calculate the number of ATEs needed. */
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if (!(MINIMAL_ATE_FLAG(paddr, req_size))) {
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ate_count = IOPG((IOPGSIZE - 1) /* worst case start offset */
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+req_size /* max mapping bytes */
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- 1) + 1; /* round UP */
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} else { /* assume requested target is page aligned */
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ate_count = IOPG(req_size /* max mapping bytes */
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- 1) + 1; /* round UP */
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}
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/* Get the number of ATEs required. */
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ate_index = pcibr_ate_alloc(pcibus_info, ate_count);
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if (ate_index < 0)
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return 0;
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/* In PCI-X mode, Prefetch not supported */
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if (IS_PCIX(pcibus_info))
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ate_flags &= ~(PCI32_ATE_PREF);
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if (SN_DMA_ADDRTYPE(dma_flags == SN_DMA_ADDR_PHYS))
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xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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else
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xio_addr = paddr;
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offset = IOPGOFF(xio_addr);
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ate = ate_flags | (xio_addr - offset);
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/* If PIC, put the targetid in the ATE */
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if (IS_PIC_SOFT(pcibus_info)) {
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ate |= (pcibus_info->pbi_hub_xid << PIC_ATE_TARGETID_SHFT);
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}
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/*
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* If we're mapping for MSI, set the MSI bit in the ATE. If it's a
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* TIOCP based pci bus, we also need to set the PIO bit in the ATE.
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*/
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if (dma_flags & SN_DMA_MSI) {
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ate |= PCI32_ATE_MSI;
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if (IS_TIOCP_SOFT(pcibus_info))
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ate |= PCI32_ATE_PIO;
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}
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ate_write(pcibus_info, ate_index, ate_count, ate);
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/*
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* Set up the DMA mapped Address.
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*/
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pci_addr = PCI32_MAPPED_BASE + offset + IOPGSIZE * ate_index;
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/*
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* If swap was set in device in pcibr_endian_set()
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* we need to turn swapping on.
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*/
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if (pcibus_info->pbi_devreg[internal_device] & PCIBR_DEV_SWAP_DIR)
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ATE_SWAP_ON(pci_addr);
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return pci_addr;
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}
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static dma_addr_t
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pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
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u64 dma_attributes, int dma_flags)
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{
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struct pcibus_info *pcibus_info = (struct pcibus_info *)
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((info->pdi_host_pcidev_info)->pdi_pcibus_info);
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u64 pci_addr;
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/* Translate to Crosstalk View of Physical Address */
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if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
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pci_addr = IS_PIC_SOFT(pcibus_info) ?
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PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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else
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pci_addr = paddr;
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pci_addr |= dma_attributes;
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/* Handle Bus mode */
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if (IS_PCIX(pcibus_info))
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pci_addr &= ~PCI64_ATTR_PREF;
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/* Handle Bridge Chipset differences */
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if (IS_PIC_SOFT(pcibus_info)) {
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pci_addr |=
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((u64) pcibus_info->
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pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
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} else
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pci_addr |= (dma_flags & SN_DMA_MSI) ?
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TIOCP_PCI64_CMDTYPE_MSI :
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TIOCP_PCI64_CMDTYPE_MEM;
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/* If PCI mode, func zero uses VCHAN0, every other func uses VCHAN1 */
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if (!IS_PCIX(pcibus_info) && PCI_FUNC(info->pdi_linux_pcidev->devfn))
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pci_addr |= PCI64_ATTR_VIRTUAL;
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return pci_addr;
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}
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static dma_addr_t
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pcibr_dmatrans_direct32(struct pcidev_info * info,
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u64 paddr, size_t req_size, u64 flags, int dma_flags)
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{
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struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
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struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
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pdi_pcibus_info;
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u64 xio_addr;
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u64 xio_base;
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u64 offset;
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u64 endoff;
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if (IS_PCIX(pcibus_info)) {
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return 0;
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}
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if (dma_flags & SN_DMA_MSI)
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return 0;
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if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
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xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
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PHYS_TO_TIODMA(paddr);
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else
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xio_addr = paddr;
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xio_base = pcibus_info->pbi_dir_xbase;
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offset = xio_addr - xio_base;
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endoff = req_size + offset;
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if ((req_size > (1ULL << 31)) || /* Too Big */
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(xio_addr < xio_base) || /* Out of range for mappings */
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(endoff > (1ULL << 31))) { /* Too Big */
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return 0;
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}
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return PCI32_DIRECT_BASE | offset;
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}
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/*
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* Wrapper routine for freeing DMA maps
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* DMA mappings for Direct 64 and 32 do not have any DMA maps.
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*/
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void
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pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
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{
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
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struct pcibus_info *pcibus_info =
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(struct pcibus_info *)pcidev_info->pdi_pcibus_info;
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if (IS_PCI32_MAPPED(dma_handle)) {
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int ate_index;
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ate_index =
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IOPG((ATE_SWAP_OFF(dma_handle) - PCI32_MAPPED_BASE));
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pcibr_ate_free(pcibus_info, ate_index);
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}
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}
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/*
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* On SN systems there is a race condition between a PIO read response and
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* DMA's. In rare cases, the read response may beat the DMA, causing the
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* driver to think that data in memory is complete and meaningful. This code
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* eliminates that race. This routine is called by the PIO read routines
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* after doing the read. For PIC this routine then forces a fake interrupt
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* on another line, which is logically associated with the slot that the PIO
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* is addressed to. It then spins while watching the memory location that
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* the interrupt is targetted to. When the interrupt response arrives, we
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* are sure that the DMA has landed in memory and it is safe for the driver
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* to proceed. For TIOCP use the Device(x) Write Request Buffer Flush
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* Bridge register since it ensures the data has entered the coherence domain,
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* unlike the PIC Device(x) Write Request Buffer Flush register.
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*/
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void sn_dma_flush(u64 addr)
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{
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nasid_t nasid;
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int is_tio;
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int wid_num;
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int i, j;
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unsigned long flags;
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u64 itte;
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struct hubdev_info *hubinfo;
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struct sn_flush_device_kernel *p;
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struct sn_flush_device_common *common;
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struct sn_flush_nasid_entry *flush_nasid_list;
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if (!sn_ioif_inited)
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return;
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nasid = NASID_GET(addr);
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if (-1 == nasid_to_cnodeid(nasid))
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return;
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hubinfo = (NODEPDA(nasid_to_cnodeid(nasid)))->pdinfo;
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BUG_ON(!hubinfo);
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flush_nasid_list = &hubinfo->hdi_flush_nasid_list;
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if (flush_nasid_list->widget_p == NULL)
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return;
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is_tio = (nasid & 1);
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if (is_tio) {
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int itte_index;
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if (TIO_HWIN(addr))
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itte_index = 0;
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else if (TIO_BWIN_WINDOWNUM(addr))
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itte_index = TIO_BWIN_WINDOWNUM(addr);
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else
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itte_index = -1;
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if (itte_index >= 0) {
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itte = flush_nasid_list->iio_itte[itte_index];
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if (! TIO_ITTE_VALID(itte))
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return;
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wid_num = TIO_ITTE_WIDGET(itte);
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} else
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wid_num = TIO_SWIN_WIDGETNUM(addr);
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} else {
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if (BWIN_WINDOWNUM(addr)) {
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itte = flush_nasid_list->iio_itte[BWIN_WINDOWNUM(addr)];
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wid_num = IIO_ITTE_WIDGET(itte);
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} else
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wid_num = SWIN_WIDGETNUM(addr);
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}
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if (flush_nasid_list->widget_p[wid_num] == NULL)
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return;
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p = &flush_nasid_list->widget_p[wid_num][0];
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/* find a matching BAR */
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for (i = 0; i < DEV_PER_WIDGET; i++,p++) {
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common = p->common;
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for (j = 0; j < PCI_ROM_RESOURCE; j++) {
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if (common->sfdl_bar_list[j].start == 0)
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break;
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if (addr >= common->sfdl_bar_list[j].start
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&& addr <= common->sfdl_bar_list[j].end)
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break;
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}
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if (j < PCI_ROM_RESOURCE && common->sfdl_bar_list[j].start != 0)
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break;
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}
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/* if no matching BAR, return without doing anything. */
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if (i == DEV_PER_WIDGET)
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return;
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/*
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* For TIOCP use the Device(x) Write Request Buffer Flush Bridge
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* register since it ensures the data has entered the coherence
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* domain, unlike PIC.
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*/
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if (is_tio) {
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/*
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* Note: devices behind TIOCE should never be matched in the
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* above code, and so the following code is PIC/CP centric.
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* If CE ever needs the sn_dma_flush mechanism, we will have
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* to account for that here and in tioce_bus_fixup().
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*/
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u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
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u32 revnum = XWIDGET_PART_REV_NUM(tio_id);
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/* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
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if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
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return;
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} else {
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pcireg_wrb_flush_get(common->sfdl_pcibus_info,
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(common->sfdl_slot - 1));
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}
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} else {
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spin_lock_irqsave(&p->sfdl_flush_lock, flags);
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*common->sfdl_flush_addr = 0;
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/* force an interrupt. */
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*(volatile u32 *)(common->sfdl_force_int_addr) = 1;
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/* wait for the interrupt to come back. */
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while (*(common->sfdl_flush_addr) != 0x10f)
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cpu_relax();
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/* okay, everything is synched up. */
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spin_unlock_irqrestore(&p->sfdl_flush_lock, flags);
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}
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return;
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}
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/*
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* DMA interfaces. Called from pci_dma.c routines.
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*/
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dma_addr_t
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pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size, int dma_flags)
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{
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dma_addr_t dma_handle;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
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/* SN cannot support DMA addresses smaller than 32 bits. */
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if (hwdev->dma_mask < 0x7fffffff) {
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return 0;
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}
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if (hwdev->dma_mask == ~0UL) {
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/*
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* Handle the most common case: 64 bit cards. This
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* call should always succeed.
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*/
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dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
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PCI64_ATTR_PREF, dma_flags);
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} else {
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/* Handle 32-63 bit cards via direct mapping */
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dma_handle = pcibr_dmatrans_direct32(pcidev_info, phys_addr,
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size, 0, dma_flags);
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if (!dma_handle) {
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/*
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* It is a 32 bit card and we cannot do direct mapping,
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* so we use an ATE.
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*/
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dma_handle = pcibr_dmamap_ate32(pcidev_info, phys_addr,
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size, PCI32_ATE_PREF,
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dma_flags);
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}
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}
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return dma_handle;
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}
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dma_addr_t
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pcibr_dma_map_consistent(struct pci_dev * hwdev, unsigned long phys_addr,
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size_t size, int dma_flags)
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{
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dma_addr_t dma_handle;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
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if (hwdev->dev.coherent_dma_mask == ~0UL) {
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dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
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PCI64_ATTR_BAR, dma_flags);
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} else {
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dma_handle = (dma_addr_t) pcibr_dmamap_ate32(pcidev_info,
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phys_addr, size,
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PCI32_ATE_BAR, dma_flags);
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}
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return dma_handle;
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}
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EXPORT_SYMBOL(sn_dma_flush);
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