176 lines
5.0 KiB
C
176 lines
5.0 KiB
C
/*
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* file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
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* based on:
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* author:
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*
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* created:
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* description:
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* blackfin serial driver head file
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#include <linux/serial.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
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#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
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#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
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#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
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#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
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#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
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#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
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#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
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#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
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#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
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#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
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#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
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#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
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#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
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#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
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#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
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#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
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#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
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#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
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#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
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#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
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#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
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#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
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#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
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#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
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#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
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defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
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# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
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#endif
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#define BFIN_UART_TX_FIFO_SIZE 2
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/*
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* The pin configuration is different from schematic
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*/
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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int status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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int tx_count;
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struct circ_buf rx_dma_buf;
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struct timer_list rx_dma_timer;
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int rx_dma_nrows;
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unsigned int tx_dma_channel;
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unsigned int rx_dma_channel;
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struct work_struct tx_dma_workqueue;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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int scts;
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int cts_pin;
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int rts_pin;
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#endif
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};
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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int uart_status_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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int uart_cts_pin;
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int uart_rts_pin;
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#endif
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};
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struct bfin_serial_res bfin_serial_resource[] = {
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#ifdef CONFIG_SERIAL_BFIN_UART0
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{
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0xFFC00400,
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IRQ_UART0_RX,
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IRQ_UART0_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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0,
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0,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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{
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0xFFC02000,
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IRQ_UART1_RX,
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IRQ_UART1_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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GPIO_PE10,
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GPIO_PE9,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART2
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{
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0xFFC02100,
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IRQ_UART2_RX,
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IRQ_UART2_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART2_TX,
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CH_UART2_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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0,
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0,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART3
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{
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0xFFC03100,
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IRQ_UART3_RX,
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IRQ_UART3_ERROR,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART3_TX,
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CH_UART3_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
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GPIO_PB3,
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GPIO_PB2,
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#endif
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},
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#endif
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};
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#define DRIVER_NAME "bfin-uart"
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