169 lines
4.2 KiB
C
169 lines
4.2 KiB
C
/*
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* Memory MAP
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* Common header file for blackfin BF561 of processors.
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*/
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#ifndef _MEM_MAP_561_H_
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#define _MEM_MAP_561_H_
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#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
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#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
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/* Async Memory Banks */
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#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
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#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
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#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
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#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
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#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
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/* Boot ROM Memory */
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#define BOOT_ROM_START 0xEF000000
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#define BOOT_ROM_LENGTH 0x800
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/* Level 1 Memory */
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#ifdef CONFIG_BFIN_ICACHE
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#define BFIN_ICACHESIZE (16*1024)
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#else
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#define BFIN_ICACHESIZE (0*1024)
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#endif
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/* Memory Map for ADSP-BF561 processors */
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#ifdef CONFIG_BF561
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#define COREA_L1_CODE_START 0xFFA00000
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#define COREA_L1_DATA_A_START 0xFF800000
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#define COREA_L1_DATA_B_START 0xFF900000
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#define COREB_L1_CODE_START 0xFF600000
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#define COREB_L1_DATA_A_START 0xFF400000
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#define COREB_L1_DATA_B_START 0xFF500000
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#define L1_CODE_START COREA_L1_CODE_START
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#define L1_DATA_A_START COREA_L1_DATA_A_START
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#define L1_DATA_B_START COREA_L1_DATA_B_START
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#define L1_CODE_LENGTH 0x4000
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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#endif
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/* Level 2 Memory */
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#define L2_START 0xFEB00000
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#define L2_LENGTH 0x20000
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/* Scratch Pad Memory */
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#define COREA_L1_SCRATCH_START 0xFFB00000
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#define COREB_L1_SCRATCH_START 0xFF700000
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#define L1_SCRATCH_START COREA_L1_SCRATCH_START
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#define L1_SCRATCH_LENGTH 0x1000
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#ifdef __ASSEMBLY__
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/*
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* The following macros both return the address of the PDA for the
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* current core.
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*
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* In its first safe (and hairy) form, the macro neither clobbers any
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* register aside of the output Preg, nor uses the stack, since it
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* could be called with an invalid stack pointer, or the current stack
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* space being uncovered by any CPLB (e.g. early exception handling).
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*
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* The constraints on the second form are a bit relaxed, and the code
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* is allowed to use the specified Dreg for determining the PDA
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* address to be returned into Preg.
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*/
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#ifdef CONFIG_SMP
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#define GET_PDA_SAFE(preg) \
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preg.l = lo(DSPID); \
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preg.h = hi(DSPID); \
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preg = [preg]; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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preg = preg << 2; \
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if cc jump 2f; \
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cc = preg == 0x0; \
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preg.l = _cpu_pda; \
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preg.h = _cpu_pda; \
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if !cc jump 3f; \
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1: \
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/* preg = 0x0; */ \
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cc = !cc; /* restore cc to 0 */ \
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jump 4f; \
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2: \
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cc = preg == 0x0; \
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preg.l = _cpu_pda; \
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preg.h = _cpu_pda; \
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if cc jump 4f; \
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/* preg = 0x1000000; */ \
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cc = !cc; /* restore cc to 1 */ \
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3: \
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preg = [preg]; \
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4:
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#define GET_PDA(preg, dreg) \
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preg.l = lo(DSPID); \
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preg.h = hi(DSPID); \
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dreg = [preg]; \
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preg.l = _cpu_pda; \
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preg.h = _cpu_pda; \
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cc = bittst(dreg, 0); \
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if !cc jump 1f; \
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preg = [preg]; \
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1: \
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#define GET_CPUID(preg, dreg) \
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preg.l = lo(DSPID); \
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preg.h = hi(DSPID); \
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dreg = [preg]; \
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dreg = ROT dreg BY -1; \
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dreg = CC;
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#else
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#define GET_PDA_SAFE(preg) \
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preg.l = _cpu_pda; \
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preg.h = _cpu_pda;
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#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
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#endif /* CONFIG_SMP */
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#endif /* __ASSEMBLY__ */
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#endif /* _MEM_MAP_533_H_ */
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