510 lines
13 KiB
C
510 lines
13 KiB
C
/*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Support functions for the ST40 PCI hardware.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <asm/pci.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h> /* irqreturn_t */
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#include "pci-st40.h"
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/* This is in P2 of course */
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#define ST40PCI_BASE_ADDRESS (0xb0000000)
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#define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0)
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#define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000)
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#define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000)
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#define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
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#define ST40PCI_REG_INDEXED(reg, index) \
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(ST40PCI_REG(reg##0) + \
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((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index))
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#define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
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#define ST40PCI_WRITE_INDEXED(reg, index, val) \
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writel((val), ST40PCI_REG_INDEXED(reg, index));
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#define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
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#define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
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#define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
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#define ST40PCI_SERR_IRQ 64
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#define ST40PCI_ERR_IRQ 65
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/* Macros to extract PLL params */
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#define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff )
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#define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
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#define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
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#define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
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/* Build up the appropriate settings */
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#define PLL_SET(mdiv,ndiv,pdiv,setup) \
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( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
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#define PLLPCICR (0xbb040000+0x10)
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#define PLLPCICR_POWERON (1<<28)
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#define PLLPCICR_OUT_EN (1<<29)
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#define PLLPCICR_LOCKSELECT (1<<30)
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#define PLLPCICR_LOCK (1<<31)
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#define PLL_25MHZ 0x793c8512
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#define PLL_33MHZ PLL_SET(18,88,3,295)
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static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
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unsigned long pciOffset, unsigned long regionSize);
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/*
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* The pcibios_map_platform_irq function is defined in the appropriate
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* board specific code and referenced here
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*/
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extern int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
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static __init void SetPCIPLL(void)
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{
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{
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/* Lets play with the PLL values */
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unsigned long pll1cr1;
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unsigned long mdiv, ndiv, pdiv;
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unsigned long muxcr;
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unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 };
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unsigned int freq;
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#define CLKGENA 0xbb040000
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#define CLKGENA_PLL2_MUXCR CLKGENA + 0x48
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pll1cr1 = ctrl_inl(PLLPCICR);
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printk("PLL1CR1 %08lx\n", pll1cr1);
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mdiv = PLL_MDIV(pll1cr1);
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ndiv = PLL_NDIV(pll1cr1);
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pdiv = PLL_PDIV(pll1cr1);
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printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv);
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freq = ((2*27*ndiv)/mdiv) / (1 << pdiv);
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printk("PLL freq %dMHz\n", freq);
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muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR);
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printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]);
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}
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}
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struct pci_err {
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unsigned mask;
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const char *error_string;
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};
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static struct pci_err int_error[]={
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{ INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"},
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{ INT_TTADI, "TTADI: Illegal byte enable in I/O transfer"},
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{ INT_TMTO, "TMTO: Target memory read/write timeout"},
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{ INT_MDEI, "MDEI: Master function disable error"},
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{ INT_APEDI, "APEDI: Address parity error"},
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{ INT_SDI, "SDI: SERR detected"},
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{ INT_DPEITW, "DPEITW: Data parity error target write"},
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{ INT_PEDITR, "PEDITR: PERR detected"},
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{ INT_TADIM, "TADIM: Target abort detected"},
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{ INT_MADIM, "MADIM: Master abort detected"},
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{ INT_MWPDI, "MWPDI: PERR from target at data write"},
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{ INT_MRDPEI, "MRDPEI: Master read data parity error"}
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};
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#define NUM_PCI_INT_ERRS (sizeof(int_error)/sizeof(struct pci_err))
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static struct pci_err aint_error[]={
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{ AINT_MBI, "MBI: Master broken"},
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{ AINT_TBTOI, "TBTOI: Target bus timeout"},
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{ AINT_MBTOI, "MBTOI: Master bus timeout"},
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{ AINT_TAI, "TAI: Target abort"},
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{ AINT_MAI, "MAI: Master abort"},
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{ AINT_RDPEI, "RDPEI: Read data parity"},
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{ AINT_WDPE, "WDPE: Write data parity"}
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};
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#define NUM_PCI_AINT_ERRS (sizeof(aint_error)/sizeof(struct pci_err))
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static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors)
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{
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int i;
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for(i=0;i<num_errors;i++) {
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if(reg & error[i].mask) {
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printk("%s\n",error[i].error_string);
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}
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}
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}
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static char * pci_commands[16]={
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"Int Ack",
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"Special Cycle",
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"I/O Read",
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"I/O Write",
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"Reserved",
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"Reserved",
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"Memory Read",
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"Memory Write",
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"Reserved",
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"Reserved",
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"Configuration Read",
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"Configuration Write",
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"Memory Read Multiple",
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"Dual Address Cycle",
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"Memory Read Line",
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"Memory Write-and-Invalidate"
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};
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static irqreturn_t st40_pci_irq(int irq, void *dev_instance, struct pt_regs *regs)
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{
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unsigned pci_int, pci_air, pci_cir, pci_aint;
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static int count=0;
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pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT);
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pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR);
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/* Reset state to stop multiple interrupts */
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ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0);
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if(++count>1) return IRQ_HANDLED;
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printk("** PCI ERROR **\n");
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if(pci_int) {
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printk("** INT register status\n");
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print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS);
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}
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if(pci_aint) {
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printk("** AINT register status\n");
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print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS);
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}
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printk("** Address and command info\n");
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printk("** Command %s : Address 0x%x\n",
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pci_commands[pci_cir&0xf],pci_air);
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if(pci_cir&CIR_PIOTEM) {
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printk("CIR_PIOTEM:PIO transfer error for master\n");
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}
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if(pci_cir&CIR_RWTET) {
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printk("CIR_RWTET:Read/Write transfer error for target\n");
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}
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return IRQ_HANDLED;
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}
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/* Rounds a number UP to the nearest power of two. Used for
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* sizing the PCI window.
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*/
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static u32 r2p2(u32 num)
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{
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int i = 31;
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u32 tmp = num;
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if (num == 0)
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return 0;
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do {
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if (tmp & (1 << 31))
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break;
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i--;
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tmp <<= 1;
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} while (i >= 0);
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tmp = 1 << i;
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/* If the original number isn't a power of 2, round it up */
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if (tmp != num)
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tmp <<= 1;
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return tmp;
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}
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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printk("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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int __init st40pci_init(unsigned memStart, unsigned memSize)
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{
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u32 lsr0;
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SetPCIPLL();
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/* Initialises the ST40 pci subsystem, performing a reset, then programming
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* up the address space decoders appropriately
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*/
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/* Should reset core here as well methink */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
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/* Loop while core resets */
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while (ST40PCI_READ(CR) & CR_SOFT_RESET);
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/* Switch off interrupts */
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ST40PCI_WRITE(INTM, 0);
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ST40PCI_WRITE(AINT, 0);
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/* Now, lets reset all the cards on the bus with extreme prejudice */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
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udelay(250);
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/* Set bus active, take it out of reset */
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ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE);
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/* The PCI spec says that no access must be made to the bus until 1 second
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* after reset. This seem ludicrously long, but some delay is needed here
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*/
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mdelay(1000);
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/* Switch off interrupts */
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ST40PCI_WRITE(INTM, 0);
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ST40PCI_WRITE(AINT, 0);
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/* Allow it to be a master */
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ST40PCI_WRITE_SHORT(CSR_CMD,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_IO);
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/* Accesse to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
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* on the PCI bus. This allows a nice 1-1 bus to phys mapping.
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*/
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ST40PCI_WRITE(MBR, 0x10000000);
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/* Always set the max size 128M (actually, it is only 96MB wide) */
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ST40PCI_WRITE(MBMR, 0x07ff0000);
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/* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
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* allow cards that have legacy io such as vga to function correctly. This gives a
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* maximum of 64K of io/space as only the bottom 16 bits of the address are copied
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* over to the bus when the transaction is made. 64K of io space is more than enough
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*/
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ST40PCI_WRITE(IOBR, 0x0);
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/* Set up the 64K window */
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ST40PCI_WRITE(IOBMR, 0x0);
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/* Now we set up the mbars so the PCI bus can see the local memory */
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/* Expose a 256M window starting at PCI address 0... */
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ST40PCI_WRITE(CSR_MBAR0, 0);
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ST40PCI_WRITE(LSR0, 0x0fff0001);
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/* ... and set up the initial incomming window to expose all of RAM */
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pci_set_rbar_region(7, memStart, memStart, memSize);
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/* Maximise timeout values */
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ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
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ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
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ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
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ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);
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return 1;
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}
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char * __init pcibios_setup(char *str)
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{
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return str;
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}
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#define SET_CONFIG_BITS(bus,devfn,where)\
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(((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
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#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
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static int CheckForMasterAbort(void)
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{
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if (ST40PCI_READ(INT) & INT_MADIM) {
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/* Should we clear config space version as well ??? */
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ST40PCI_WRITE(INT, INT_MADIM);
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ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
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return 1;
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}
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return 0;
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}
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/* Write to config register */
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static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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{
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ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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*val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
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break;
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case 2:
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*val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
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break;
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case 4:
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*val = ST40PCI_READ(PDR);
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break;
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}
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if (CheckForMasterAbort()){
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switch (size) {
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case 1:
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*val = (u8)0xff;
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break;
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case 2:
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*val = (u16)0xffff;
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break;
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case 4:
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*val = 0xffffffff;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
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{
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ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
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break;
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case 2:
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ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
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break;
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case 4:
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ST40PCI_WRITE(PDR, val);
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break;
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}
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CheckForMasterAbort();
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops st40pci_config_ops = {
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.read = st40pci_read,
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.write = st40pci_write,
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};
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/* Everything hangs off this */
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static struct pci_bus *pci_root_bus;
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static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
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{
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return PCI_SLOT(dev->devfn);
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}
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static int __init pcibios_init(void)
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{
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extern unsigned long memory_start, memory_end;
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printk(KERN_ALERT "pci-st40.c: pcibios_init\n");
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if (sh_mv.mv_init_pci != NULL) {
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sh_mv.mv_init_pci();
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}
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/* The pci subsytem needs to know where memory is and how much
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* of it there is. I've simply made these globals. A better mechanism
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* is probably needed.
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*/
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st40pci_init(PHYSADDR(memory_start),
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PHYSADDR(memory_end) - PHYSADDR(memory_start));
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if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
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SA_INTERRUPT, "st40pci", NULL)) {
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printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
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return -EIO;
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}
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/* Enable the PCI interrupts on the device */
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ST40PCI_WRITE(INTM, ~0);
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ST40PCI_WRITE(AINT, ~0);
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/* Map the io address apprioately */
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#ifdef CONFIG_HD64465
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hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
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ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
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#endif
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/* ok, do the scan man */
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pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL);
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pci_assign_unassigned_resources();
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pci_fixup_irqs(no_swizzle, pcibios_map_platform_irq);
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return 0;
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}
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subsys_initcall(pcibios_init);
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void __init pcibios_fixup_bus(struct pci_bus *bus)
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{
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}
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/*
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* Publish a region of local address space over the PCI bus
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* to other devices.
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*/
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static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
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unsigned long pciOffset, unsigned long regionSize)
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{
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unsigned long mask;
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if (region > 7)
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return;
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if (regionSize > (512 * 1024 * 1024))
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return;
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mask = r2p2(regionSize) - 0x10000;
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/* Diable the region (in case currently in use, should never happen) */
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ST40PCI_WRITE_INDEXED(RSR, region, 0);
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/* Start of local address space to publish */
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ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );
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/* Start of region in PCI address space as an offset from MBAR0 */
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ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);
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/* Size of region */
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ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
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}
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