5a226c6f5c
The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures. However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.
One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.
glibc is hardcoded to expect the registers to be there.
The way atomic ops are done through these registers is straightforward:
(1) Write the address of the word you wish to access into AARU. This causes
the CPU to go and fetch that word and load it into ADRU. The status bits
are also cleared in ASRU.
(2) The current data value is read from the ADRU register and modified.
(3) To alter the data in RAM, the revised data is written back to the ADRU
register, which causes the CPU to attempt to write it back.
(4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
must be checked to confirm that the operation wasn't aborted. If any of
the watches have been set to true, the operation was aborted.
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
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| .. | ||
| Kconfig.cache | ||
| Makefile | ||
| cache-disabled.c | ||
| cache-flush-by-reg.S | ||
| cache-flush-by-tag.S | ||
| cache-flush-icache.c | ||
| cache-inv-by-reg.S | ||
| cache-inv-by-tag.S | ||
| cache-inv-icache.c | ||
| cache-smp-flush.c | ||
| cache-smp-inv.c | ||
| cache-smp.c | ||
| cache-smp.h | ||
| cache.c | ||
| dma-alloc.c | ||
| extable.c | ||
| fault.c | ||
| init.c | ||
| misalignment.c | ||
| mmu-context.c | ||
| pgtable.c | ||
| tlb-mn10300.S | ||
| tlb-smp.c | ||