403 lines
10 KiB
C
403 lines
10 KiB
C
/*
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* arch/arm/mach-ixp2000/ixdp2x01.c
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*
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* Code common to Intel IXDP2401 and IXDP2801 platforms
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*
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* Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright (C) 2002-2003 Intel Corp.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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/*************************************************************************
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* IXDP2x01 IRQ Handling
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*************************************************************************/
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static void ixdp2x01_irq_mask(unsigned int irq)
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{
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ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
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IXP2000_BOARD_IRQ_MASK(irq));
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}
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static void ixdp2x01_irq_unmask(unsigned int irq)
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{
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ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
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IXP2000_BOARD_IRQ_MASK(irq));
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}
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static u32 valid_irq_mask;
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static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
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{
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u32 ex_interrupt;
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int i;
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desc->chip->mask(irq);
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ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
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if (!ex_interrupt) {
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printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
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return;
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}
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for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
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if (ex_interrupt & (1 << i)) {
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struct irqdesc *cpld_desc;
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int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
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cpld_desc = irq_desc + cpld_irq;
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desc_handle_irq(cpld_irq, cpld_desc, regs);
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}
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}
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desc->chip->unmask(irq);
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}
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static struct irqchip ixdp2x01_irq_chip = {
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.mask = ixdp2x01_irq_mask,
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.ack = ixdp2x01_irq_mask,
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.unmask = ixdp2x01_irq_unmask
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};
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/*
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* We only do anything if we are the master NPU on the board.
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* The slave NPU only has the ethernet chip going directly to
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* the PCIB interrupt input.
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*/
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void __init ixdp2x01_init_irq(void)
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{
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int irq = 0;
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/* initialize chip specific interrupts */
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ixp2000_init_irq();
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if (machine_is_ixdp2401())
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valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
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else
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valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
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/* Mask all interrupts from CPLD, disable simulation */
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ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
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ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
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for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
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if (irq & valid_irq_mask) {
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set_irq_chip(irq, &ixdp2x01_irq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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} else {
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set_irq_flags(irq, 0);
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}
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}
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/* Hook into PCI interrupts */
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set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
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}
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/*************************************************************************
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* IXDP2x01 memory map and serial ports
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*************************************************************************/
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static struct map_desc ixdp2x01_io_desc __initdata = {
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.virtual = IXDP2X01_VIRT_CPLD_BASE,
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.pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
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.length = IXDP2X01_CPLD_REGION_SIZE,
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.type = MT_DEVICE
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};
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static struct uart_port ixdp2x01_serial_ports[2] = {
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{
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.membase = (char *)(IXDP2X01_UART1_VIRT_BASE),
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.mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
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.irq = IRQ_IXDP2X01_UART1,
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.flags = UPF_SKIP_TEST,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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.uartclk = IXDP2X01_UART_CLK,
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.line = 1,
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.type = PORT_16550A,
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.fifosize = 16
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}, {
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.membase = (char *)(IXDP2X01_UART2_VIRT_BASE),
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.mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
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.irq = IRQ_IXDP2X01_UART2,
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.flags = UPF_SKIP_TEST,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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.uartclk = IXDP2X01_UART_CLK,
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.line = 2,
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.type = PORT_16550A,
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.fifosize = 16
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},
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};
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static void __init ixdp2x01_map_io(void)
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{
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ixp2000_map_io();
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iotable_init(&ixdp2x01_io_desc, 1);
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early_serial_setup(&ixdp2x01_serial_ports[0]);
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early_serial_setup(&ixdp2x01_serial_ports[1]);
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}
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/*************************************************************************
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* IXDP2x01 timer tick configuration
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*************************************************************************/
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static unsigned int ixdp2x01_clock;
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static int __init ixdp2x01_clock_setup(char *str)
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{
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ixdp2x01_clock = simple_strtoul(str, NULL, 10);
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return 1;
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}
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__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
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static void __init ixdp2x01_timer_init(void)
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{
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if (!ixdp2x01_clock)
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ixdp2x01_clock = 50000000;
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ixp2000_init_time(ixdp2x01_clock);
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}
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static struct sys_timer ixdp2x01_timer = {
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.init = ixdp2x01_timer_init,
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.offset = ixp2000_gettimeoffset,
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};
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/*************************************************************************
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* IXDP2x01 PCI
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*************************************************************************/
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void __init ixdp2x01_pci_preinit(void)
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{
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ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
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ixp2000_pci_preinit();
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}
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#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
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static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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u8 bus = dev->bus->number;
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u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
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struct pci_bus *tmp_bus = dev->bus;
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/* Primary bus, no interrupts here */
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if (bus == 0) {
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return -1;
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}
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/* Lookup first leaf in bus tree */
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while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
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tmp_bus = tmp_bus->parent;
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}
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/* Select between known bridges */
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switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
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/* Device is located after first MB bridge */
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case 0x0008:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after first MB bridge */
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switch (devpin) {
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case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
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if (machine_is_ixdp2401())
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return IRQ_IXDP2401_INTA_82546;
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return -1;
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case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
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if (machine_is_ixdp2401())
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return IRQ_IXDP2401_INTB_82546;
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return -1;
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case DEVPIN(0, 1): /* PMC INTA# */
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return IRQ_IXDP2X01_SPCI_PMC_INTA;
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case DEVPIN(0, 2): /* PMC INTB# */
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return IRQ_IXDP2X01_SPCI_PMC_INTB;
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case DEVPIN(0, 3): /* PMC INTC# */
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return IRQ_IXDP2X01_SPCI_PMC_INTC;
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case DEVPIN(0, 4): /* PMC INTD# */
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return IRQ_IXDP2X01_SPCI_PMC_INTD;
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}
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}
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break;
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case 0x0010:
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if (tmp_bus == dev->bus) {
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/* Device is located directy after second MB bridge */
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/* Secondary bus of second bridge */
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switch (devpin) {
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case DEVPIN(0, 1): /* DB#0 */
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return IRQ_IXDP2X01_SPCI_DB_0;
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case DEVPIN(1, 1): /* DB#1 */
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return IRQ_IXDP2X01_SPCI_DB_1;
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}
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} else {
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/* Device is located indirectly after second MB bridge */
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/* Not supported now */
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}
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break;
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}
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return -1;
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}
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static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
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{
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sys->mem_offset = 0xe0000000;
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if (machine_is_ixdp2801())
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sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
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return ixp2000_pci_setup(nr, sys);
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}
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struct hw_pci ixdp2x01_pci __initdata = {
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.nr_controllers = 1,
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.setup = ixdp2x01_pci_setup,
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.preinit = ixdp2x01_pci_preinit,
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.scan = ixp2000_pci_scan_bus,
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.map_irq = ixdp2x01_pci_map_irq,
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};
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int __init ixdp2x01_pci_init(void)
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{
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pci_common_init(&ixdp2x01_pci);
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return 0;
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}
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subsys_initcall(ixdp2x01_pci_init);
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/*************************************************************************
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* IXDP2x01 Machine Intialization
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*************************************************************************/
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static struct flash_platform_data ixdp2x01_flash_platform_data = {
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.map_name = "cfi_probe",
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.width = 1,
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};
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static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
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{
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ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
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((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
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return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
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}
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static struct ixp2000_flash_data ixdp2x01_flash_data = {
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.platform_data = &ixdp2x01_flash_platform_data,
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.bank_setup = ixdp2x01_flash_bank_setup
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};
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static struct resource ixdp2x01_flash_resource = {
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.start = 0xc4000000,
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.end = 0xc4000000 + 0x01ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ixdp2x01_flash = {
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.name = "IXP2000-Flash",
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.id = 0,
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.dev = {
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.platform_data = &ixdp2x01_flash_data,
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},
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.num_resources = 1,
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.resource = &ixdp2x01_flash_resource,
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};
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static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
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.sda_pin = IXDP2X01_GPIO_SDA,
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.scl_pin = IXDP2X01_GPIO_SCL,
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};
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static struct platform_device ixdp2x01_i2c_controller = {
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.name = "IXP2000-I2C",
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.id = 0,
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.dev = {
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.platform_data = &ixdp2x01_i2c_gpio_pins,
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},
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.num_resources = 0
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};
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static struct platform_device *ixdp2x01_devices[] __initdata = {
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&ixdp2x01_flash,
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&ixdp2x01_i2c_controller
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};
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static void __init ixdp2x01_init_machine(void)
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{
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ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
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(IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
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ixdp2x01_flash_data.nr_banks =
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((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
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platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
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ixp2000_uart_init();
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}
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#ifdef CONFIG_ARCH_IXDP2401
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MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.phys_io = IXP2000_UART_PHYS_BASE,
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.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = ixdp2x01_map_io,
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.init_irq = ixdp2x01_init_irq,
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.timer = &ixdp2x01_timer,
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.init_machine = ixdp2x01_init_machine,
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MACHINE_END
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#endif
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#ifdef CONFIG_ARCH_IXDP2801
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MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.phys_io = IXP2000_UART_PHYS_BASE,
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.io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = ixdp2x01_map_io,
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.init_irq = ixdp2x01_init_irq,
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.timer = &ixdp2x01_timer,
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.init_machine = ixdp2x01_init_machine,
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MACHINE_END
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#endif
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