137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* Copyright (C) 2005 Philips Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
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*/
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#define MAX_DUM_CHANNELS 64
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#define RGB_MEM_WINDOW(x) (0x10000000 + (x)*0x00100000)
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#define QCIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x30000: -1)
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#define CIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x60000: -1)
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#define CTRL_SETDIRTY (0x00000001)
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#define CONF_DIRTYENABLE (0x00000020)
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#define CONF_SYNCENABLE (0x00000004)
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#define DIRTY_ENABLED(conf) ((conf) & 0x0020)
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#define SYNC_ENABLED(conf) ((conf) & 0x0004)
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/* Display 1 & 2 Write Timing Configuration */
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#define PNX4008_DUM_WT_CFG 0x00372000
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/* Display 1 & 2 Read Timing Configuration */
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#define PNX4008_DUM_RT_CFG 0x00003A47
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/* DUM Transit State Timing Configuration */
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#define PNX4008_DUM_T_CFG 0x1D /* 29 HCLK cycles */
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/* DUM Sync count clock divider */
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#define PNX4008_DUM_CLK_DIV 0x02DD
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/* Memory size for framebuffer, allocated through dma_alloc_writecombine().
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* Must be PAGE aligned
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*/
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#define FB_DMA_SIZE (PAGE_ALIGN(SZ_1M + PAGE_SIZE))
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#define OFFSET_RGBBUFFER (0xB0000)
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#define OFFSET_YUVBUFFER (0x00000)
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#define YUVBUFFER (lcd_video_start + OFFSET_YUVBUFFER)
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#define RGBBUFFER (lcd_video_start + OFFSET_RGBBUFFER)
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#define CMDSTRING_BASEADDR (0x00C000) /* iram */
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#define BYTES_PER_CMDSTRING (0x80)
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#define NR_OF_CMDSTRINGS (64)
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#define MAX_NR_PRESTRINGS (0x40)
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#define MAX_NR_POSTSTRINGS (0x40)
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/* various mask definitions */
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#define DUM_CLK_ENABLE 0x01
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#define DUM_CLK_DISABLE 0
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#define DUM_DECODE_MASK 0x1FFFFFFF
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#define DUM_CHANNEL_CFG_MASK 0x01FF
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#define DUM_CHANNEL_CFG_SYNC_MASK 0xFFFE00FF
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#define DUM_CHANNEL_CFG_SYNC_MASK_SET 0x0CA00
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#define SDUM_RETURNVAL_BASE (0x500)
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#define CONF_SYNC_OFF (0x602)
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#define CONF_SYNC_ON (0x603)
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#define CONF_DIRTYDETECTION_OFF (0x600)
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#define CONF_DIRTYDETECTION_ON (0x601)
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struct dumchannel_uf {
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int channelnr;
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u32 *dirty;
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u32 *source;
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u32 x_offset;
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u32 y_offset;
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u32 width;
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u32 height;
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};
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enum {
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FB_TYPE_YUV,
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FB_TYPE_RGB
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};
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struct cmdstring {
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int channelnr;
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uint16_t prestringlen;
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uint16_t poststringlen;
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uint16_t format;
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uint16_t reserved;
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uint16_t startaddr_low;
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uint16_t startaddr_high;
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uint16_t pixdatlen_low;
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uint16_t pixdatlen_high;
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u32 precmd[MAX_NR_PRESTRINGS];
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u32 postcmd[MAX_NR_POSTSTRINGS];
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};
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struct dumchannel {
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int channelnr;
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int dum_ch_min;
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int dum_ch_max;
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int dum_ch_conf;
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int dum_ch_stat;
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int dum_ch_ctrl;
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};
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int pnx4008_alloc_dum_channel(int dev_id);
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int pnx4008_free_dum_channel(int channr, int dev_id);
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int pnx4008_get_dum_channel_uf(struct dumchannel_uf *pChan_uf, int dev_id);
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int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id);
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int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id);
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int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id);
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int pnx4008_force_dum_update_channel(int channr, int dev_id);
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int pnx4008_get_dum_channel_config(int channr, int dev_id);
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int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma, struct device *dev);
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int pnx4008_set_dum_exit_notification(int dev_id);
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int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
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dma_addr_t * phys_addr, int *fb_length);
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