311 lines
7.2 KiB
C
311 lines
7.2 KiB
C
/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/prom.h>
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#include <asm/mpic.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc85xx.h"
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#ifdef CONFIG_CPM2
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#include <linux/fs_enet_pd.h>
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#include <asm/cpm2.h>
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#include <sysdev/cpm2_pic.h>
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#include <asm/fs_pd.h>
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#endif
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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#ifdef CONFIG_PCI
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int
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mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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void __init
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mpc85xx_pcibios_fixup(void)
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{
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struct pci_dev *dev = NULL;
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for_each_pci_dev(dev)
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pci_read_irq_line(dev);
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}
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_CPM2
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static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
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{
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int cascade_irq;
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while ((cascade_irq = cpm2_get_irq()) >= 0) {
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generic_handle_irq(cascade_irq);
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}
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desc->chip->eoi(irq);
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}
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#endif /* CONFIG_CPM2 */
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void __init mpc85xx_ads_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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#ifdef CONFIG_CPM2
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int irq;
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#endif
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np = of_find_node_by_type(np, "open-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if(of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Could not map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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4, 0, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_assign_isu(mpic, 0, r.start + 0x10200);
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mpic_assign_isu(mpic, 1, r.start + 0x10280);
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mpic_assign_isu(mpic, 2, r.start + 0x10300);
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mpic_assign_isu(mpic, 3, r.start + 0x10380);
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mpic_assign_isu(mpic, 4, r.start + 0x10400);
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mpic_assign_isu(mpic, 5, r.start + 0x10480);
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mpic_assign_isu(mpic, 6, r.start + 0x10500);
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mpic_assign_isu(mpic, 7, r.start + 0x10580);
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/* Unused on this platform (leave room for 8548) */
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mpic_assign_isu(mpic, 8, r.start + 0x10600);
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mpic_assign_isu(mpic, 9, r.start + 0x10680);
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mpic_assign_isu(mpic, 10, r.start + 0x10700);
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mpic_assign_isu(mpic, 11, r.start + 0x10780);
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/* External Interrupts */
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mpic_assign_isu(mpic, 12, r.start + 0x10000);
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mpic_assign_isu(mpic, 13, r.start + 0x10080);
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mpic_assign_isu(mpic, 14, r.start + 0x10100);
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mpic_init(mpic);
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#ifdef CONFIG_CPM2
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/* Setup CPM2 PIC */
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np = of_find_node_by_type(NULL, "cpm-pic");
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if (np == NULL) {
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printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
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return;
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}
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irq = irq_of_parse_and_map(np, 0);
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cpm2_pic_init(np);
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set_irq_chained_handler(irq, cpm2_cascade);
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#endif
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}
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/*
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* Setup the architecture
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*/
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#ifdef CONFIG_CPM2
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void init_fcc_ioports(struct fs_platform_info *fpi)
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{
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struct io_port *io = cpm2_map(im_ioport);
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int fcc_no = fs_get_fcc_index(fpi->fs_no);
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int target;
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u32 tempval;
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switch(fcc_no) {
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case 1:
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB2_DIRB0;
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tempval |= PB2_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB2_PSORB0;
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tempval |= PB2_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB2_DIRB0 | PB2_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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target = CPM_CLK_FCC2;
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break;
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case 2:
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tempval = in_be32(&io->iop_pdirb);
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tempval &= ~PB3_DIRB0;
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tempval |= PB3_DIRB1;
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out_be32(&io->iop_pdirb, tempval);
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tempval = in_be32(&io->iop_psorb);
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tempval &= ~PB3_PSORB0;
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tempval |= PB3_PSORB1;
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out_be32(&io->iop_psorb, tempval);
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tempval = in_be32(&io->iop_pparb);
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tempval |= (PB3_DIRB0 | PB3_DIRB1);
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out_be32(&io->iop_pparb, tempval);
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tempval = in_be32(&io->iop_pdirc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= PC3_DIRC1;
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out_be32(&io->iop_pparc, tempval);
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target = CPM_CLK_FCC3;
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break;
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default:
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printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
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return;
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}
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/* Port C has clocks...... */
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tempval = in_be32(&io->iop_psorc);
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tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
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out_be32(&io->iop_psorc, tempval);
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tempval = in_be32(&io->iop_pdirc);
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tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
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out_be32(&io->iop_pdirc, tempval);
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tempval = in_be32(&io->iop_pparc);
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tempval |= (PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
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out_be32(&io->iop_pparc, tempval);
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cpm2_unmap(io);
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/* Configure Serial Interface clock routing.
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* First, clear FCC bits to zero,
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* then set the ones we want.
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*/
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cpm2_clk_setup(target, fpi->clk_rx, CPM_CLK_RX);
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cpm2_clk_setup(target, fpi->clk_tx, CPM_CLK_TX);
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}
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#endif
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static void __init mpc85xx_ads_setup_arch(void)
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{
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struct device_node *cpu;
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
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cpu = of_find_node_by_type(NULL, "cpu");
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if (cpu != 0) {
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const unsigned int *fp;
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fp = get_property(cpu, "clock-frequency", NULL);
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if (fp != 0)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 50000000 / HZ;
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of_node_put(cpu);
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}
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#ifdef CONFIG_CPM2
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cpm2_reset();
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#endif
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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add_bridge(np);
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ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup;
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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}
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void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: mpc85xx\n");
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_ads_probe(void)
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{
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/* We always match for now, eventually we should look at the flat
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dev tree to ensure this is the board we are suppose to run on
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*/
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return 1;
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}
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define_machine(mpc85xx_ads) {
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.name = "MPC85xx ADS",
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.probe = mpc85xx_ads_probe,
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.setup_arch = mpc85xx_ads_setup_arch,
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.init_IRQ = mpc85xx_ads_pic_init,
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.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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