338 lines
9.2 KiB
C
338 lines
9.2 KiB
C
/*****************************************************************************
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* Copyright 2003 - 2009 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#ifndef NAND_BCM_UMI_H
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#define NAND_BCM_UMI_H
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/* ---- Include Files ---------------------------------------------------- */
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#include <mach/reg_umi.h>
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#include <mach/reg_nand.h>
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#include <cfg_global.h>
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/* ---- Constants and Types ---------------------------------------------- */
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#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
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#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
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#else
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#define NAND_ECC_BCH 0
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#endif
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#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES 13
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#if NAND_ECC_BCH
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#ifdef BOOT0_BUILD
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#define NAND_ECC_NUM_BYTES 13
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#else
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#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
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#endif
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#else
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#define NAND_ECC_NUM_BYTES 3
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#endif
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#define NAND_DATA_ACCESS_SIZE 512
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/* ---- Variable Externs ------------------------------------------ */
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/* ---- Function Prototypes --------------------------------------- */
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int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
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int numEccBytes);
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/* Check in device is ready */
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static inline int nand_bcm_umi_dev_ready(void)
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{
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return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
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}
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/* Wait until device is ready */
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static inline void nand_bcm_umi_wait_till_ready(void)
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{
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while (nand_bcm_umi_dev_ready() == 0)
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;
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}
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/* Enable Hamming ECC */
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static inline void nand_bcm_umi_hamming_enable_hwecc(void)
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{
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/* disable and reset ECC, 512 byte page */
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REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
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REG_UMI_NAND_ECC_CSR_256BYTE);
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/* enable ECC */
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REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
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}
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#if NAND_ECC_BCH
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/* BCH ECC specifics */
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#define ECC_BITS_PER_CORRECTABLE_BIT 13
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/* Enable BCH Read ECC */
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static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
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{
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/* disable and reset ECC */
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REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
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/* Turn on ECC */
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REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
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}
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/* Enable BCH Write ECC */
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static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
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{
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/* disable and reset ECC */
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REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
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/* Turn on ECC */
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REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
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}
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/* Config number of BCH ECC bytes */
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static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
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{
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uint32_t nValue;
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uint32_t tValue;
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uint32_t kValue;
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uint32_t numBits = numEccBytes * 8;
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/* disable and reset ECC */
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REG_UMI_BCH_CTRL_STATUS =
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REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
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REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
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/* Every correctible bit requires 13 ECC bits */
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tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
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/* Total data in number of bits for generating and computing BCH ECC */
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nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
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/* K parameter is used internally. K = N - (T * 13) */
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kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
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/* Write the settings */
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REG_UMI_BCH_N = nValue;
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REG_UMI_BCH_T = tValue;
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REG_UMI_BCH_K = kValue;
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}
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/* Pause during ECC read calculation to skip bytes in OOB */
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static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
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{
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REG_UMI_BCH_CTRL_STATUS =
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REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
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REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
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}
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/* Resume during ECC read calculation after skipping bytes in OOB */
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static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
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{
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REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
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}
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/* Poll read ECC calc to check when hardware completes */
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static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
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{
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uint32_t regVal;
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do {
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/* wait for ECC to be valid */
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regVal = REG_UMI_BCH_CTRL_STATUS;
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} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
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return regVal;
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}
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/* Poll write ECC calc to check when hardware completes */
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static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
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{
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/* wait for ECC to be valid */
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while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
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== 0)
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;
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}
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/* Read the OOB and ECC, for kernel write OOB to a buffer */
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#if defined(__KERNEL__) && !defined(STANDALONE)
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static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
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uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
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#else
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static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
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uint8_t *eccCalc, int numEccBytes)
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#endif
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{
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int eccPos = 0;
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int numToRead = 16; /* There are 16 bytes per sector in the OOB */
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/* ECC is already paused when this function is called */
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if (pageSize != NAND_DATA_ACCESS_SIZE) {
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/* skip BI */
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#if defined(__KERNEL__) && !defined(STANDALONE)
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*oobp++ = REG_NAND_DATA8;
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#else
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REG_NAND_DATA8;
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#endif
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numToRead--;
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}
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while (numToRead > numEccBytes) {
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/* skip free oob region */
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#if defined(__KERNEL__) && !defined(STANDALONE)
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*oobp++ = REG_NAND_DATA8;
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#else
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REG_NAND_DATA8;
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#endif
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numToRead--;
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}
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if (pageSize == NAND_DATA_ACCESS_SIZE) {
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/* read ECC bytes before BI */
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nand_bcm_umi_bch_resume_read_ecc_calc();
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while (numToRead > 11) {
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#if defined(__KERNEL__) && !defined(STANDALONE)
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*oobp = REG_NAND_DATA8;
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eccCalc[eccPos++] = *oobp;
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oobp++;
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#else
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eccCalc[eccPos++] = REG_NAND_DATA8;
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#endif
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numToRead--;
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}
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nand_bcm_umi_bch_pause_read_ecc_calc();
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if (numToRead == 11) {
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/* read BI */
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#if defined(__KERNEL__) && !defined(STANDALONE)
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*oobp++ = REG_NAND_DATA8;
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#else
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REG_NAND_DATA8;
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#endif
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numToRead--;
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}
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}
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/* read ECC bytes */
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nand_bcm_umi_bch_resume_read_ecc_calc();
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while (numToRead) {
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#if defined(__KERNEL__) && !defined(STANDALONE)
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*oobp = REG_NAND_DATA8;
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eccCalc[eccPos++] = *oobp;
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oobp++;
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#else
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eccCalc[eccPos++] = REG_NAND_DATA8;
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#endif
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numToRead--;
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}
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}
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/* Helper function to write ECC */
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static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
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uint8_t *oobp, uint8_t eccVal)
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{
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if (eccBytePos <= numEccBytes)
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*oobp = eccVal;
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}
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/* Write OOB with ECC */
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static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
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uint8_t *oobp, int numEccBytes)
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{
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uint32_t eccVal = 0xffffffff;
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/* wait for write ECC to be valid */
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nand_bcm_umi_bch_poll_write_ecc_calc();
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/*
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** Get the hardware ecc from the 32-bit result registers.
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** Read after 512 byte accesses. Format B3B2B1B0
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** where B3 = ecc3, etc.
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*/
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if (pageSize == NAND_DATA_ACCESS_SIZE) {
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/* Now fill in the ECC bytes */
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if (numEccBytes >= 13)
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eccVal = REG_UMI_BCH_WR_ECC_3;
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/* Usually we skip CM in oob[0,1] */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
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(eccVal >> 16) & 0xff);
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
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(eccVal >> 8) & 0xff);
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/* Write ECC in oob[2,3,4] */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
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eccVal & 0xff); /* ECC 12 */
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if (numEccBytes >= 9)
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eccVal = REG_UMI_BCH_WR_ECC_2;
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
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(eccVal >> 24) & 0xff); /* ECC11 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
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(eccVal >> 16) & 0xff); /* ECC10 */
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/* Always Skip BI in oob[5] */
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} else {
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/* Always Skip BI in oob[0] */
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/* Now fill in the ECC bytes */
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if (numEccBytes >= 13)
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eccVal = REG_UMI_BCH_WR_ECC_3;
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/* Usually skip CM in oob[1,2] */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
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(eccVal >> 16) & 0xff);
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
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(eccVal >> 8) & 0xff);
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/* Write ECC in oob[3-15] */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
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eccVal & 0xff); /* ECC12 */
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if (numEccBytes >= 9)
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eccVal = REG_UMI_BCH_WR_ECC_2;
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
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(eccVal >> 24) & 0xff); /* ECC11 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
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(eccVal >> 16) & 0xff); /* ECC10 */
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}
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/* Fill in the remainder of ECC locations */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
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(eccVal >> 8) & 0xff); /* ECC9 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
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eccVal & 0xff); /* ECC8 */
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if (numEccBytes >= 5)
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eccVal = REG_UMI_BCH_WR_ECC_1;
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
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(eccVal >> 24) & 0xff); /* ECC7 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
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(eccVal >> 16) & 0xff); /* ECC6 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
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(eccVal >> 8) & 0xff); /* ECC5 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
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eccVal & 0xff); /* ECC4 */
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if (numEccBytes >= 1)
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eccVal = REG_UMI_BCH_WR_ECC_0;
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
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(eccVal >> 24) & 0xff); /* ECC3 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
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(eccVal >> 16) & 0xff); /* ECC2 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
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(eccVal >> 8) & 0xff); /* ECC1 */
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NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
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eccVal & 0xff); /* ECC0 */
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}
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#endif
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#endif /* NAND_BCM_UMI_H */
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