518 lines
14 KiB
C
518 lines
14 KiB
C
/*
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* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <mach/control.h>
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#include <mach/dma.h>
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#include <mach/mcbsp.h>
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#include "omap-mcbsp.h"
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#include "omap-pcm.h"
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#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
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struct omap_mcbsp_data {
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unsigned int bus_id;
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struct omap_mcbsp_reg_cfg regs;
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unsigned int fmt;
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/*
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* Flags indicating is the bus already activated and configured by
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* another substream
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*/
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int active;
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int configured;
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};
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#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
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static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
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/*
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* Stream DMA parameters. DMA request line and port address are set runtime
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* since they are different between OMAP1 and later OMAPs
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*/
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static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
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#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
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static const int omap1_dma_reqs[][2] = {
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{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
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{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
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{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
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};
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static const unsigned long omap1_mcbsp_port[][2] = {
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{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
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};
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#else
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static const int omap1_dma_reqs[][2] = {};
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static const unsigned long omap1_mcbsp_port[][2] = {};
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#endif
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#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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static const int omap24xx_dma_reqs[][2] = {
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{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
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{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
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{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
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{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
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{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
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#endif
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};
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#else
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static const int omap24xx_dma_reqs[][2] = {};
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#endif
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#if defined(CONFIG_ARCH_OMAP2420)
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static const unsigned long omap2420_mcbsp_port[][2] = {
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{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
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};
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#else
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static const unsigned long omap2420_mcbsp_port[][2] = {};
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#endif
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#if defined(CONFIG_ARCH_OMAP2430)
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static const unsigned long omap2430_mcbsp_port[][2] = {
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{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
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OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
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OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
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};
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#else
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static const unsigned long omap2430_mcbsp_port[][2] = {};
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#endif
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#if defined(CONFIG_ARCH_OMAP34XX)
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static const unsigned long omap34xx_mcbsp_port[][2] = {
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{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
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};
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#else
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static const unsigned long omap34xx_mcbsp_port[][2] = {};
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#endif
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static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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int err = 0;
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if (!cpu_dai->active)
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err = omap_mcbsp_request(mcbsp_data->bus_id);
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return err;
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}
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static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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if (!cpu_dai->active) {
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omap_mcbsp_free(mcbsp_data->bus_id);
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mcbsp_data->configured = 0;
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}
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}
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static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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int err = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!mcbsp_data->active++)
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omap_mcbsp_start(mcbsp_data->bus_id);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (!--mcbsp_data->active)
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omap_mcbsp_stop(mcbsp_data->bus_id);
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break;
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default:
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err = -EINVAL;
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}
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return err;
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}
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static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
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int wlen, channels;
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unsigned long port;
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if (cpu_class_is_omap1()) {
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dma = omap1_dma_reqs[bus_id][substream->stream];
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port = omap1_mcbsp_port[bus_id][substream->stream];
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} else if (cpu_is_omap2420()) {
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dma = omap24xx_dma_reqs[bus_id][substream->stream];
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port = omap2420_mcbsp_port[bus_id][substream->stream];
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} else if (cpu_is_omap2430()) {
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dma = omap24xx_dma_reqs[bus_id][substream->stream];
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port = omap2430_mcbsp_port[bus_id][substream->stream];
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} else if (cpu_is_omap343x()) {
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dma = omap24xx_dma_reqs[bus_id][substream->stream];
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port = omap34xx_mcbsp_port[bus_id][substream->stream];
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} else {
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return -ENODEV;
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}
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omap_mcbsp_dai_dma_params[id][substream->stream].name =
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substream->stream ? "Audio Capture" : "Audio Playback";
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omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
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omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
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cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
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if (mcbsp_data->configured) {
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/* McBSP already configured by another stream */
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return 0;
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}
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channels = params_channels(params);
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switch (channels) {
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case 2:
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/* Use dual-phase frames */
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regs->rcr2 |= RPHASE;
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regs->xcr2 |= XPHASE;
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case 1:
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/* Set 1 word per (McBSP) frame */
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regs->rcr2 |= RFRLEN2(1 - 1);
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regs->rcr1 |= RFRLEN1(1 - 1);
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regs->xcr2 |= XFRLEN2(1 - 1);
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regs->xcr1 |= XFRLEN1(1 - 1);
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break;
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default:
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/* Unsupported number of channels */
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return -EINVAL;
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}
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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/* Set word lengths */
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wlen = 16;
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regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
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regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
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regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
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regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
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break;
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default:
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/* Unsupported PCM format */
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return -EINVAL;
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}
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/* Set FS period and length in terms of bit clock periods */
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switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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regs->srgr2 |= FPER(wlen * 2 - 1);
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regs->srgr1 |= FWID(wlen - 1);
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break;
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case SND_SOC_DAIFMT_DSP_B:
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regs->srgr2 |= FPER(wlen * channels - 1);
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regs->srgr1 |= FWID(wlen * channels - 2);
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break;
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}
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omap_mcbsp_config(bus_id, &mcbsp_data->regs);
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mcbsp_data->configured = 1;
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return 0;
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}
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/*
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* This must be called before _set_clkdiv and _set_sysclk since McBSP register
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* cache is initialized here
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*/
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static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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if (mcbsp_data->configured)
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return 0;
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mcbsp_data->fmt = fmt;
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memset(regs, 0, sizeof(*regs));
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/* Generic McBSP register settings */
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regs->spcr2 |= XINTM(3) | FREE;
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regs->spcr1 |= RINTM(3);
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regs->rcr2 |= RFIG;
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regs->xcr2 |= XFIG;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* 1-bit data delay */
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regs->rcr2 |= RDATDLY(1);
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regs->xcr2 |= XDATDLY(1);
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* 0-bit data delay */
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regs->rcr2 |= RDATDLY(0);
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regs->xcr2 |= XDATDLY(0);
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break;
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default:
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/* Unsupported data format */
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* McBSP master. Set FS and bit clocks as outputs */
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regs->pcr0 |= FSXM | FSRM |
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CLKXM | CLKRM;
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/* Sample rate generator drives the FS */
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regs->srgr2 |= FSGM;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* McBSP slave */
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break;
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default:
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/* Unsupported master/slave configuration */
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return -EINVAL;
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}
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/* Set bit clock (CLKX/CLKR) and FS polarities */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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/*
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* Normal BCLK + FS.
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* FS active low. TX data driven on falling edge of bit clock
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* and RX data sampled on rising edge of bit clock.
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*/
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regs->pcr0 |= FSXP | FSRP |
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CLKXP | CLKRP;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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regs->pcr0 |= CLKXP | CLKRP;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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regs->pcr0 |= FSXP | FSRP;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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if (div_id != OMAP_MCBSP_CLKGDV)
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return -ENODEV;
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regs->srgr1 |= CLKGDV(div - 1);
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return 0;
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}
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static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
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int clk_id)
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{
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int sel_bit;
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u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
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if (cpu_class_is_omap1()) {
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/* OMAP1's can use only external source clock */
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if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
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return -EINVAL;
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else
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return 0;
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}
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if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
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return -EINVAL;
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if (cpu_is_omap343x())
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reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
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switch (mcbsp_data->bus_id) {
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case 0:
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reg = OMAP2_CONTROL_DEVCONF0;
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sel_bit = 2;
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break;
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case 1:
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reg = OMAP2_CONTROL_DEVCONF0;
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sel_bit = 6;
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break;
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case 2:
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reg = reg_devconf1;
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sel_bit = 0;
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break;
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case 3:
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reg = reg_devconf1;
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sel_bit = 2;
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break;
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case 4:
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reg = reg_devconf1;
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sel_bit = 4;
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break;
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default:
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return -EINVAL;
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}
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if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
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omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
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else
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omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
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return 0;
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}
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static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq,
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int dir)
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{
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struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
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struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
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int err = 0;
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switch (clk_id) {
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case OMAP_MCBSP_SYSCLK_CLK:
|
|
regs->srgr2 |= CLKSM;
|
|
break;
|
|
case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
|
|
case OMAP_MCBSP_SYSCLK_CLKS_EXT:
|
|
err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
|
|
break;
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLKX_EXT:
|
|
regs->srgr2 |= CLKSM;
|
|
case OMAP_MCBSP_SYSCLK_CLKR_EXT:
|
|
regs->pcr0 |= SCLKME;
|
|
break;
|
|
default:
|
|
err = -ENODEV;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
#define OMAP_MCBSP_DAI_BUILDER(link_id) \
|
|
{ \
|
|
.name = "omap-mcbsp-dai-"#link_id, \
|
|
.id = (link_id), \
|
|
.playback = { \
|
|
.channels_min = 1, \
|
|
.channels_max = 2, \
|
|
.rates = OMAP_MCBSP_RATES, \
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
|
|
}, \
|
|
.capture = { \
|
|
.channels_min = 1, \
|
|
.channels_max = 2, \
|
|
.rates = OMAP_MCBSP_RATES, \
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
|
|
}, \
|
|
.ops = { \
|
|
.startup = omap_mcbsp_dai_startup, \
|
|
.shutdown = omap_mcbsp_dai_shutdown, \
|
|
.trigger = omap_mcbsp_dai_trigger, \
|
|
.hw_params = omap_mcbsp_dai_hw_params, \
|
|
.set_fmt = omap_mcbsp_dai_set_dai_fmt, \
|
|
.set_clkdiv = omap_mcbsp_dai_set_clkdiv, \
|
|
.set_sysclk = omap_mcbsp_dai_set_dai_sysclk, \
|
|
}, \
|
|
.private_data = &mcbsp_data[(link_id)].bus_id, \
|
|
}
|
|
|
|
struct snd_soc_dai omap_mcbsp_dai[] = {
|
|
OMAP_MCBSP_DAI_BUILDER(0),
|
|
OMAP_MCBSP_DAI_BUILDER(1),
|
|
#if NUM_LINKS >= 3
|
|
OMAP_MCBSP_DAI_BUILDER(2),
|
|
#endif
|
|
#if NUM_LINKS == 5
|
|
OMAP_MCBSP_DAI_BUILDER(3),
|
|
OMAP_MCBSP_DAI_BUILDER(4),
|
|
#endif
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
|
|
|
|
static int __init snd_omap_mcbsp_init(void)
|
|
{
|
|
return snd_soc_register_dais(omap_mcbsp_dai,
|
|
ARRAY_SIZE(omap_mcbsp_dai));
|
|
}
|
|
module_init(snd_omap_mcbsp_init);
|
|
|
|
static void __exit snd_omap_mcbsp_exit(void)
|
|
{
|
|
snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
|
|
}
|
|
module_exit(snd_omap_mcbsp_exit);
|
|
|
|
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
|
|
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
|
|
MODULE_LICENSE("GPL");
|