168 lines
4.4 KiB
C
168 lines
4.4 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mipsregs.h>
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#include <asm/ptrace.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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unsigned long cpu_khz;
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#if defined(CONFIG_MIPS_SEAD)
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#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5)
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#else
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#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
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#endif
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#if defined(CONFIG_MIPS_ATLAS)
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static char display_string[] = " LINUX ON ATLAS ";
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#endif
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#if defined(CONFIG_MIPS_MALTA)
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static char display_string[] = " LINUX ON MALTA ";
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#endif
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#if defined(CONFIG_MIPS_SEAD)
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static char display_string[] = " LINUX ON SEAD ";
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#endif
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static unsigned int display_count = 0;
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#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
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#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
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static unsigned int timer_tick_count=0;
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void mips_timer_interrupt(struct pt_regs *regs)
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{
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if ((timer_tick_count++ % HZ) == 0) {
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mips_display_message(&display_string[display_count++]);
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if (display_count == MAX_DISPLAY_COUNT)
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display_count = 0;
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}
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ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs);
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}
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/*
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* Estimate CPU frequency. Sets mips_counter_frequency as a side-effect
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*/
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static unsigned int __init estimate_cpu_frequency(void)
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{
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unsigned int prid = read_c0_prid() & 0xffff00;
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unsigned int count;
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#ifdef CONFIG_MIPS_SEAD
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/*
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* The SEAD board doesn't have a real time clock, so we can't
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* really calculate the timer frequency
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* For now we hardwire the SEAD board frequency to 12MHz.
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*/
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if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
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(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count = 12000000;
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else
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count = 6000000;
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#endif
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#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
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unsigned int flags;
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Start r4k counter. */
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write_c0_count(0);
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/* Read counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count();
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/* restore interrupts */
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local_irq_restore(flags);
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#endif
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mips_hpt_frequency = count;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count *= 2;
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count += 5000; /* round */
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count -= count%10000;
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return count;
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}
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unsigned long __init mips_rtc_get_time(void)
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{
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return mc146818_get_cmos_time();
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}
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void __init mips_time_init(void)
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{
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unsigned int est_freq, flags;
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local_irq_save(flags);
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#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
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/* Set Data mode - binary. */
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CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
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#endif
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est_freq = estimate_cpu_frequency ();
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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cpu_khz = est_freq / 1000;
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local_irq_restore(flags);
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}
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void __init mips_timer_setup(struct irqaction *irq)
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{
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/* we are using the cpu counter for timer interrupts */
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irq->handler = no_action; /* we use our own handler */
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setup_irq(MIPS_CPU_TIMER_IRQ, irq);
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/* to generate the first timer interrupt */
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write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
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set_c0_status(ALLINTS);
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}
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