237 lines
10 KiB
C
237 lines
10 KiB
C
/*
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* IBM eServer eHCA Infiniband device driver for Linux on POWER
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*
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* pSeries interface definitions
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*
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* Authors: Waleri Fomin <fomin@de.ibm.com>
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* Christoph Raisch <raisch@de.ibm.com>
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*
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* Copyright (c) 2005 IBM Corporation
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*
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* All rights reserved.
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*
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* This source code is distributed under a dual license of GPL v2.0 and OpenIB
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* BSD.
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*
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* OpenIB BSD License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __EHCA_CLASSES_PSERIES_H__
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#define __EHCA_CLASSES_PSERIES_H__
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#include "hcp_phyp.h"
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#include "ipz_pt_fn.h"
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struct ehca_pfqp {
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struct ipz_qpt sqpt;
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struct ipz_qpt rqpt;
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};
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struct ehca_pfcq {
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struct ipz_qpt qpt;
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u32 cqnr;
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};
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struct ehca_pfeq {
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struct ipz_qpt qpt;
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struct h_galpa galpa;
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u32 eqnr;
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};
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struct ipz_adapter_handle {
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u64 handle;
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};
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struct ipz_cq_handle {
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u64 handle;
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};
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struct ipz_eq_handle {
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u64 handle;
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};
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struct ipz_qp_handle {
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u64 handle;
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};
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struct ipz_mrmw_handle {
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u64 handle;
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};
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struct ipz_pd {
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u32 value;
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};
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struct hcp_modify_qp_control_block {
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u32 qkey; /* 00 */
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u32 rdd; /* reliable datagram domain */
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u32 send_psn; /* 02 */
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u32 receive_psn; /* 03 */
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u32 prim_phys_port; /* 04 */
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u32 alt_phys_port; /* 05 */
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u32 prim_p_key_idx; /* 06 */
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u32 alt_p_key_idx; /* 07 */
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u32 rdma_atomic_ctrl; /* 08 */
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u32 qp_state; /* 09 */
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u32 reserved_10; /* 10 */
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u32 rdma_nr_atomic_resp_res; /* 11 */
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u32 path_migration_state; /* 12 */
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u32 rdma_atomic_outst_dest_qp; /* 13 */
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u32 dest_qp_nr; /* 14 */
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u32 min_rnr_nak_timer_field; /* 15 */
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u32 service_level; /* 16 */
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u32 send_grh_flag; /* 17 */
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u32 retry_count; /* 18 */
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u32 timeout; /* 19 */
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u32 path_mtu; /* 20 */
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u32 max_static_rate; /* 21 */
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u32 dlid; /* 22 */
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u32 rnr_retry_count; /* 23 */
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u32 source_path_bits; /* 24 */
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u32 traffic_class; /* 25 */
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u32 hop_limit; /* 26 */
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u32 source_gid_idx; /* 27 */
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u32 flow_label; /* 28 */
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u32 reserved_29; /* 29 */
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union { /* 30 */
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u64 dw[2];
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u8 byte[16];
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} dest_gid;
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u32 service_level_al; /* 34 */
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u32 send_grh_flag_al; /* 35 */
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u32 retry_count_al; /* 36 */
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u32 timeout_al; /* 37 */
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u32 max_static_rate_al; /* 38 */
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u32 dlid_al; /* 39 */
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u32 rnr_retry_count_al; /* 40 */
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u32 source_path_bits_al; /* 41 */
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u32 traffic_class_al; /* 42 */
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u32 hop_limit_al; /* 43 */
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u32 source_gid_idx_al; /* 44 */
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u32 flow_label_al; /* 45 */
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u32 reserved_46; /* 46 */
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u32 reserved_47; /* 47 */
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union { /* 48 */
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u64 dw[2];
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u8 byte[16];
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} dest_gid_al;
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u32 max_nr_outst_send_wr; /* 52 */
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u32 max_nr_outst_recv_wr; /* 53 */
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u32 disable_ete_credit_check; /* 54 */
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u32 qp_number; /* 55 */
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u64 send_queue_handle; /* 56 */
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u64 recv_queue_handle; /* 58 */
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u32 actual_nr_sges_in_sq_wqe; /* 60 */
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u32 actual_nr_sges_in_rq_wqe; /* 61 */
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u32 qp_enable; /* 62 */
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u32 curr_srq_limit; /* 63 */
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u64 qp_aff_asyn_ev_log_reg; /* 64 */
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u64 shared_rq_hndl; /* 66 */
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u64 trigg_doorbell_qp_hndl; /* 68 */
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u32 reserved_70_127[58]; /* 70 */
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};
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#define MQPCB_MASK_QKEY EHCA_BMASK_IBM( 0, 0)
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#define MQPCB_MASK_SEND_PSN EHCA_BMASK_IBM( 2, 2)
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#define MQPCB_MASK_RECEIVE_PSN EHCA_BMASK_IBM( 3, 3)
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#define MQPCB_MASK_PRIM_PHYS_PORT EHCA_BMASK_IBM( 4, 4)
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#define MQPCB_PRIM_PHYS_PORT EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_ALT_PHYS_PORT EHCA_BMASK_IBM( 5, 5)
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#define MQPCB_MASK_PRIM_P_KEY_IDX EHCA_BMASK_IBM( 6, 6)
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#define MQPCB_PRIM_P_KEY_IDX EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_ALT_P_KEY_IDX EHCA_BMASK_IBM( 7, 7)
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#define MQPCB_MASK_RDMA_ATOMIC_CTRL EHCA_BMASK_IBM( 8, 8)
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#define MQPCB_MASK_QP_STATE EHCA_BMASK_IBM( 9, 9)
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#define MQPCB_QP_STATE EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES EHCA_BMASK_IBM(11, 11)
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#define MQPCB_MASK_PATH_MIGRATION_STATE EHCA_BMASK_IBM(12, 12)
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#define MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP EHCA_BMASK_IBM(13, 13)
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#define MQPCB_MASK_DEST_QP_NR EHCA_BMASK_IBM(14, 14)
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#define MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD EHCA_BMASK_IBM(15, 15)
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#define MQPCB_MASK_SERVICE_LEVEL EHCA_BMASK_IBM(16, 16)
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#define MQPCB_MASK_SEND_GRH_FLAG EHCA_BMASK_IBM(17, 17)
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#define MQPCB_MASK_RETRY_COUNT EHCA_BMASK_IBM(18, 18)
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#define MQPCB_MASK_TIMEOUT EHCA_BMASK_IBM(19, 19)
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#define MQPCB_MASK_PATH_MTU EHCA_BMASK_IBM(20, 20)
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#define MQPCB_PATH_MTU EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_MAX_STATIC_RATE EHCA_BMASK_IBM(21, 21)
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#define MQPCB_MAX_STATIC_RATE EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_DLID EHCA_BMASK_IBM(22, 22)
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#define MQPCB_DLID EHCA_BMASK_IBM(16, 31)
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#define MQPCB_MASK_RNR_RETRY_COUNT EHCA_BMASK_IBM(23, 23)
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#define MQPCB_RNR_RETRY_COUNT EHCA_BMASK_IBM(29, 31)
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#define MQPCB_MASK_SOURCE_PATH_BITS EHCA_BMASK_IBM(24, 24)
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#define MQPCB_SOURCE_PATH_BITS EHCA_BMASK_IBM(25, 31)
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#define MQPCB_MASK_TRAFFIC_CLASS EHCA_BMASK_IBM(25, 25)
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#define MQPCB_TRAFFIC_CLASS EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_HOP_LIMIT EHCA_BMASK_IBM(26, 26)
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#define MQPCB_HOP_LIMIT EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_SOURCE_GID_IDX EHCA_BMASK_IBM(27, 27)
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#define MQPCB_SOURCE_GID_IDX EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_FLOW_LABEL EHCA_BMASK_IBM(28, 28)
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#define MQPCB_FLOW_LABEL EHCA_BMASK_IBM(12, 31)
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#define MQPCB_MASK_DEST_GID EHCA_BMASK_IBM(30, 30)
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#define MQPCB_MASK_SERVICE_LEVEL_AL EHCA_BMASK_IBM(31, 31)
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#define MQPCB_SERVICE_LEVEL_AL EHCA_BMASK_IBM(28, 31)
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#define MQPCB_MASK_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(32, 32)
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#define MQPCB_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(31, 31)
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#define MQPCB_MASK_RETRY_COUNT_AL EHCA_BMASK_IBM(33, 33)
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#define MQPCB_RETRY_COUNT_AL EHCA_BMASK_IBM(29, 31)
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#define MQPCB_MASK_TIMEOUT_AL EHCA_BMASK_IBM(34, 34)
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#define MQPCB_TIMEOUT_AL EHCA_BMASK_IBM(27, 31)
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#define MQPCB_MASK_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(35, 35)
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#define MQPCB_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_DLID_AL EHCA_BMASK_IBM(36, 36)
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#define MQPCB_DLID_AL EHCA_BMASK_IBM(16, 31)
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#define MQPCB_MASK_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(37, 37)
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#define MQPCB_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(29, 31)
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#define MQPCB_MASK_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(38, 38)
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#define MQPCB_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(25, 31)
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#define MQPCB_MASK_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(39, 39)
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#define MQPCB_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_HOP_LIMIT_AL EHCA_BMASK_IBM(40, 40)
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#define MQPCB_HOP_LIMIT_AL EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(41, 41)
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#define MQPCB_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(24, 31)
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#define MQPCB_MASK_FLOW_LABEL_AL EHCA_BMASK_IBM(42, 42)
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#define MQPCB_FLOW_LABEL_AL EHCA_BMASK_IBM(12, 31)
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#define MQPCB_MASK_DEST_GID_AL EHCA_BMASK_IBM(44, 44)
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#define MQPCB_MASK_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(45, 45)
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#define MQPCB_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(16, 31)
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#define MQPCB_MASK_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(46, 46)
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#define MQPCB_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(16, 31)
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#define MQPCB_MASK_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(47, 47)
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#define MQPCB_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(31, 31)
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#define MQPCB_QP_NUMBER EHCA_BMASK_IBM( 8, 31)
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#define MQPCB_MASK_QP_ENABLE EHCA_BMASK_IBM(48, 48)
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#define MQPCB_QP_ENABLE EHCA_BMASK_IBM(31, 31)
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#define MQPCB_MASK_CURR_SRQ_LIMIT EHCA_BMASK_IBM(49, 49)
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#define MQPCB_CURR_SRQ_LIMIT EHCA_BMASK_IBM(16, 31)
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#define MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG EHCA_BMASK_IBM(50, 50)
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#define MQPCB_MASK_SHARED_RQ_HNDL EHCA_BMASK_IBM(51, 51)
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#endif /* __EHCA_CLASSES_PSERIES_H__ */
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