286 lines
7.2 KiB
C
286 lines
7.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <asm/sn/io.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pic.h>
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#include <asm/sn/tiocp.h>
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union br_ptr {
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struct tiocp tio;
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struct pic pic;
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};
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/*
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* Control Register Access -- Read/Write 0000_0020
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*/
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void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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__sn_clrq_relaxed(&ptr->tio.cp_control, bits);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);
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break;
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default:
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panic
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("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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__sn_setq_relaxed(&ptr->tio.cp_control, bits);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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__sn_setq_relaxed(&ptr->pic.p_wid_control, bits);
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break;
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default:
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panic
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("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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/*
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* PCI/PCIX Target Flush Register Access -- Read Only 0000_0050
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*/
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u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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u64 ret = 0;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);
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break;
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default:
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panic
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("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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/* Read of the Target Flush should always return zero */
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if (ret != 0)
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panic("pcireg_tflush_get:Target Flush failed\n");
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return ret;
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}
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/*
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* Interrupt Status Register Access -- Read Only 0000_0100
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*/
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u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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u64 ret = 0;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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ret = __sn_readq_relaxed(&ptr->pic.p_int_status);
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break;
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default:
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panic
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("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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return ret;
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}
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/*
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* Interrupt Enable Register Access -- Read/Write 0000_0108
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*/
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void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
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break;
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default:
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panic
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("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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__sn_setq_relaxed(&ptr->pic.p_int_enable, bits);
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break;
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default:
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panic
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("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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/*
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* Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168
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*/
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void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
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u64 addr)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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__sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
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TIOCP_HOST_INTR_ADDR);
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__sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
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(addr & TIOCP_HOST_INTR_ADDR));
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break;
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case PCIBR_BRIDGETYPE_PIC:
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__sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
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PIC_HOST_INTR_ADDR);
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__sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
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(addr & PIC_HOST_INTR_ADDR));
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break;
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default:
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panic
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("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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/*
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* Force Interrupt Register Access -- Write Only 0000_01C0 - 0000_01F8
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*/
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void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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writeq(1, &ptr->tio.cp_force_pin[int_n]);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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writeq(1, &ptr->pic.p_force_pin[int_n]);
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break;
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default:
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panic
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("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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/*
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* Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
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*/
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u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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u64 ret = 0;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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ret =
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__sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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ret =
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__sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
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break;
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default:
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panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
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}
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}
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/* Read of the Write Buffer Flush should always return zero */
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return ret;
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}
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void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
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u64 val)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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writeq(val, &ptr->tio.cp_int_ate_ram[ate_index]);
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break;
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case PCIBR_BRIDGETYPE_PIC:
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writeq(val, &ptr->pic.p_int_ate_ram[ate_index]);
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break;
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default:
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panic
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("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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}
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u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
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{
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union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
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u64 __iomem *ret = NULL;
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if (pcibus_info) {
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switch (pcibus_info->pbi_bridge_type) {
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case PCIBR_BRIDGETYPE_TIOCP:
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ret = &ptr->tio.cp_int_ate_ram[ate_index];
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break;
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case PCIBR_BRIDGETYPE_PIC:
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ret = &ptr->pic.p_int_ate_ram[ate_index];
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break;
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default:
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panic
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("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
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ptr);
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}
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}
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return ret;
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}
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