148 lines
5.7 KiB
C
148 lines
5.7 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Galileo Evaluation Boards PCI support.
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*
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* The general-purpose functions to read/write and configure the GT64120A's
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* PCI registers (function names start with pci0 or pci1) are either direct
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* copies of functions written by Galileo Technology, or are modifications
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* of their functions to work with Linux 2.4 vs Linux 2.2. These functions
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* are Copyright - Galileo Technology.
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*
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* Other functions are derived from other MIPS PCI implementations, or were
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* written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/gt64120.h>
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#define SELF 0
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/*
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* pciXReadConfigReg - Read from a PCI configuration register
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* - Make sure the GT is configured as a master before
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* reading from another device on the PCI.
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* - The function takes care of Big/Little endian conversion.
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* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
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* spec)
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* pciDevNum: The device number needs to be addressed.
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* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
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* cause register to make sure the data is valid
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|00|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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*/
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static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
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{
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unsigned int DataForRegCf8;
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unsigned int data;
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DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
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(PCI_FUNC(device->devfn) << 8) |
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(offset & ~0x3)) | 0x80000000;
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GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
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/*
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* The casual observer might wonder why the READ is duplicated here,
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* rather than immediately following the WRITE, and just have the swap
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* in the "if". That's because there is a latency problem with trying
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* to read immediately after setting up the address register. The "if"
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* check gives enough time for the address to stabilize, so the READ
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* can work.
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*/
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if (PCI_SLOT(device->devfn) == SELF) /* This board */
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return GT_READ(GT_PCI0_CFGDATA_OFS);
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else /* PCI is little endian so swap the Data. */
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return __GT_READ(GT_PCI0_CFGDATA_OFS);
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}
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/*
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* pciXWriteConfigReg - Write to a PCI configuration register
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* - Make sure the GT is configured as a master before
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* writingto another device on the PCI.
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* - The function takes care of Big/Little endian conversion.
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* Inputs: unsigned int regOffset: The register offset as it apears in the
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* GT spec
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* (or any other PCI device spec)
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* pciDevNum: The device number needs to be addressed.
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|00|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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*/
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static void pci0WriteConfigReg(unsigned int offset,
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struct pci_dev *device, unsigned int data)
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{
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unsigned int DataForRegCf8;
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DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
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(PCI_FUNC(device->devfn) << 8) |
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(offset & ~0x3)) | 0x80000000;
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GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
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if (PCI_SLOT(device->devfn) == SELF) /* This board */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
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else /* configuration Transaction over the pci. */
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__GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
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}
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extern struct pci_ops gt64120_pci_ops;
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void __init pcibios_init(void)
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{
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u32 tmp;
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struct pci_dev controller;
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controller.devfn = SELF;
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tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
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tmp = GT_READ(GT_PCI0_BARE_OFS);
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/*
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* You have to enable bus mastering to configure any other
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* card on the bus.
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*/
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tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
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tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
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/*
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* Reset PCI I/O and PCI MEM values to ones supported by EVM.
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*/
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ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
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iomem_resource.start = GT_PCI_MEM_BASE;
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iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1;
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pci_scan_bus(0, >64120_pci_ops, NULL);
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}
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