61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
#ifndef __ASM_ARCH_PXA3XX_NAND_H
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#define __ASM_ARCH_PXA3XX_NAND_H
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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struct pxa3xx_nand_timing {
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unsigned int tCH; /* Enable signal hold time */
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unsigned int tCS; /* Enable signal setup time */
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unsigned int tWH; /* ND_nWE high duration */
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unsigned int tWP; /* ND_nWE pulse time */
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unsigned int tRH; /* ND_nRE high duration */
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unsigned int tRP; /* ND_nRE pulse width */
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unsigned int tR; /* ND_nWE high to ND_nRE low for read */
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unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
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unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
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};
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struct pxa3xx_nand_cmdset {
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uint16_t read1;
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uint16_t read2;
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uint16_t program;
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uint16_t read_status;
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uint16_t read_id;
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uint16_t erase;
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uint16_t reset;
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uint16_t lock;
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uint16_t unlock;
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uint16_t lock_status;
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};
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struct pxa3xx_nand_flash {
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const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
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const struct pxa3xx_nand_cmdset *cmdset;
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uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
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uint32_t page_size; /* Page size in bytes (PAGE_SZ) */
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uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */
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uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */
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uint32_t num_blocks; /* Number of physical blocks in Flash */
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uint32_t chip_id;
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};
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struct pxa3xx_nand_platform_data {
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/* the data flash bus is shared between the Static Memory
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* Controller and the Data Flash Controller, the arbiter
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* controls the ownership of the bus
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*/
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int enable_arbiter;
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const struct mtd_partition *parts;
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unsigned int nr_parts;
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const struct pxa3xx_nand_flash * flash;
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size_t num_flash;
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};
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extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
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#endif /* __ASM_ARCH_PXA3XX_NAND_H */
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