97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/*
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* Header file for IBM CPC700 Host Bridge, et. al.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* This file contains the defines and macros for the IBM CPC700 host bridge,
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* memory controller, PIC, UARTs, IIC, and Timers.
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*/
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#ifndef __PPC_SYSLIB_CPC700_H__
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#define __PPC_SYSLIB_CPC700_H__
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#include <linux/stddef.h>
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#include <linux/types.h>
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#include <linux/init.h>
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/* XXX no barriers? not even any volatiles? -- paulus */
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#define CPC700_OUT_32(a,d) (*(u_int *)a = d)
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#define CPC700_IN_32(a) (*(u_int *)a)
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/*
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* PCI Section
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*/
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#define CPC700_PCI_CONFIG_ADDR 0xfec00000
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#define CPC700_PCI_CONFIG_DATA 0xfec00004
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/* CPU -> PCI memory window 0 */
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#define CPC700_PMM0_LOCAL 0xff400000 /* CPU physical addr */
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#define CPC700_PMM0_MASK_ATTR 0xff400004 /* size and attrs */
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#define CPC700_PMM0_PCI_LOW 0xff400008 /* PCI addr, low word */
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#define CPC700_PMM0_PCI_HIGH 0xff40000c /* PCI addr, high wd */
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/* CPU -> PCI memory window 1 */
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#define CPC700_PMM1_LOCAL 0xff400010
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#define CPC700_PMM1_MASK_ATTR 0xff400014
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#define CPC700_PMM1_PCI_LOW 0xff400018
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#define CPC700_PMM1_PCI_HIGH 0xff40001c
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/* CPU -> PCI memory window 2 */
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#define CPC700_PMM2_LOCAL 0xff400020
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#define CPC700_PMM2_MASK_ATTR 0xff400024
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#define CPC700_PMM2_PCI_LOW 0xff400028
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#define CPC700_PMM2_PCI_HIGH 0xff40002c
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/* PCI memory -> CPU window 1 */
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#define CPC700_PTM1_MEMSIZE 0xff400030 /* window size */
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#define CPC700_PTM1_LOCAL 0xff400034 /* CPU phys addr */
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/* PCI memory -> CPU window 2 */
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#define CPC700_PTM2_MEMSIZE 0xff400038 /* size and enable */
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#define CPC700_PTM2_LOCAL 0xff40003c
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/*
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* PIC Section
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*
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* IBM calls the CPC700's programmable interrupt controller the Universal
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* Interrupt Controller or UIC.
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*/
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/*
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* UIC Register Addresses.
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*/
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#define CPC700_UIC_UICSR 0xff500880 /* Status Reg (Rd/Clr)*/
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#define CPC700_UIC_UICSRS 0xff500884 /* Status Reg (Set) */
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#define CPC700_UIC_UICER 0xff500888 /* Enable Reg */
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#define CPC700_UIC_UICCR 0xff50088c /* Critical Reg */
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#define CPC700_UIC_UICPR 0xff500890 /* Polarity Reg */
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#define CPC700_UIC_UICTR 0xff500894 /* Trigger Reg */
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#define CPC700_UIC_UICMSR 0xff500898 /* Masked Status Reg */
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#define CPC700_UIC_UICVR 0xff50089c /* Vector Reg */
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#define CPC700_UIC_UICVCR 0xff5008a0 /* Vector Config Reg */
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#define CPC700_UIC_UICER_ENABLE 0x00000001 /* Enable an IRQ */
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#define CPC700_UIC_UICVCR_31_HI 0x00000000 /* IRQ 31 hi priority */
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#define CPC700_UIC_UICVCR_0_HI 0x00000001 /* IRQ 0 hi priority */
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#define CPC700_UIC_UICVCR_BASE_MASK 0xfffffffc
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#define CPC700_UIC_UICVCR_ORDER_MASK 0x00000001
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/* Specify value of a bit for an IRQ. */
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#define CPC700_UIC_IRQ_BIT(i) ((0x00000001) << (31 - (i)))
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/*
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* UIC Exports...
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*/
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extern struct hw_interrupt_type cpc700_pic;
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extern unsigned int cpc700_irq_assigns[32][2];
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extern void __init cpc700_init_IRQ(void);
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extern int cpc700_get_irq(struct pt_regs *);
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#endif /* __PPC_SYSLIB_CPC700_H__ */
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