82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* Definitions for the IBM CPC710 PCI Host Bridge
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __PPC_PLATFORMS_CPC710_H
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#define __PPC_PLATFORMS_CPC710_H
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/* General bridge and memory controller registers */
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#define PIDR 0xff000008
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#define CNFR 0xff00000c
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#define RSTR 0xff000010
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#define UCTL 0xff001000
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#define MPSR 0xff001010
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#define SIOC 0xff001020
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#define ABCNTL 0xff001030
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#define SRST 0xff001040
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#define ERRC 0xff001050
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#define SESR 0xff001060
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#define SEAR 0xff001070
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#define SIOC1 0xff001090
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#define PGCHP 0xff001100
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#define GPDIR 0xff001130
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#define GPOUT 0xff001150
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#define ATAS 0xff001160
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#define AVDG 0xff001170
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#define MCCR 0xff001200
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#define MESR 0xff001220
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#define MEAR 0xff001230
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#define MCER0 0xff001300
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#define MCER1 0xff001310
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#define MCER2 0xff001320
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#define MCER3 0xff001330
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#define MCER4 0xff001340
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#define MCER5 0xff001350
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#define MCER6 0xff001360
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#define MCER7 0xff001370
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/*
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* PCI32/64 configuration registers
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* Given as offsets from their
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* respective physical segment BAR
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*/
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#define PIBAR 0x000f7800
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#define PMBAR 0x000f7810
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#define MSIZE 0x000f7f40
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#define IOSIZE 0x000f7f60
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#define SMBAR 0x000f7f80
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#define SIBAR 0x000f7fc0
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#define PSSIZE 0x000f8100
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#define PPSIZE 0x000f8110
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#define BARPS 0x000f8120
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#define BARPP 0x000f8130
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#define PSBAR 0x000f8140
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#define PPBAR 0x000f8150
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#define BPMDLK 0x000f8200 /* Bottom of Peripheral Memory Space */
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#define TPMDLK 0x000f8210 /* Top of Peripheral Memory Space */
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#define BIODLK 0x000f8220 /* Bottom of Peripheral I/O Space */
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#define TIODLK 0x000f8230 /* Top of Perioheral I/O Space */
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#define DLKCTRL 0x000f8240 /* Deadlock control */
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#define DLKDEV 0x000f8250 /* Deadlock device */
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/* System standard configuration registers space */
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#define DCR 0xff200000
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#define DID 0xff200004
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#define BAR 0xff200018
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/* Device specific configuration space */
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#define PCIENB 0xff201000
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/* Configuration space registers */
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#define CPC710_BUS_NUMBER 0x40
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#define CPC710_SUB_BUS_NUMBER 0x41
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#endif /* __PPC_PLATFORMS_CPC710_H */
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