516 lines
12 KiB
C
516 lines
12 KiB
C
/*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* The CardBus support is very preliminary. Preallocating space is
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* the way to go but will require some change in card services to
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* make it useful. Eventually this will ensure that we can put
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* multiple CB bridges behind multiple P2P bridges. For now, at
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* least it ensures that we place the CB bridge BAR and assigned
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* initial bus numbers. I definitely need to do something about
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* the lack of 16-bit I/O support. -MDP
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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#define PCIAUTO_IDE_MODE_MASK 0x05
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif /* DEBUG */
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static int pciauto_upper_iospc;
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static int pciauto_upper_memspc;
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void __init pciauto_setup_bars(struct pci_controller *hose,
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int current_bus,
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int pci_devfn,
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int bar_limit)
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{
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int bar_response, bar_size, bar_value;
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int bar, addr_mask;
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int * upper_limit;
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int found_mem64 = 0;
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DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
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current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
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for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
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/* Tickle the BAR and get the response */
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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bar,
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0xffffffff);
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early_read_config_dword(hose,
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current_bus,
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pci_devfn,
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bar,
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&bar_response);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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addr_mask = PCI_BASE_ADDRESS_IO_MASK;
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upper_limit = &pciauto_upper_iospc;
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DBG("PCI Autoconfig: BAR 0x%x, I/O, ", bar);
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} else {
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if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
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upper_limit = &pciauto_upper_memspc;
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DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar);
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}
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/* Calculate requested size */
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bar_size = ~(bar_response & addr_mask) + 1;
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/* Allocate a base address */
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bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
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/* Write it out and update our limit */
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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bar,
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bar_value);
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*upper_limit = bar_value;
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/*
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* If we are a 64-bit decoder then increment to the
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* upper 32 bits of the bar and force it to locate
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* in the lower 4GB of memory.
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*/
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if (found_mem64) {
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bar += 4;
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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bar,
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0x00000000);
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found_mem64 = 0;
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}
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DBG("size=0x%x, address=0x%x\n",
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bar_size, bar_value);
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}
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}
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void __init pciauto_prescan_setup_bridge(struct pci_controller *hose,
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int current_bus,
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int pci_devfn,
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int sub_bus,
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int *iosave,
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int *memsave)
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{
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/* Configure bus number registers */
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_PRIMARY_BUS,
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current_bus);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SECONDARY_BUS,
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sub_bus + 1);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SUBORDINATE_BUS,
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0xff);
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/* Round memory allocator to 1MB boundary */
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pciauto_upper_memspc &= ~(0x100000 - 1);
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*memsave = pciauto_upper_memspc;
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/* Round I/O allocator to 4KB boundary */
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pciauto_upper_iospc &= ~(0x1000 - 1);
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*iosave = pciauto_upper_iospc;
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_MEMORY_LIMIT,
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((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_IO_LIMIT,
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((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_IO_LIMIT_UPPER16,
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((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
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/* Zero upper 32 bits of prefetchable base/limit */
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_PREF_BASE_UPPER32,
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0);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_PREF_LIMIT_UPPER32,
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0);
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}
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void __init pciauto_postscan_setup_bridge(struct pci_controller *hose,
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int current_bus,
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int pci_devfn,
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int sub_bus,
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int *iosave,
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int *memsave)
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{
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int cmdstat;
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/* Configure bus number registers */
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SUBORDINATE_BUS,
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sub_bus);
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/*
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* Round memory allocator to 1MB boundary.
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* If no space used, allocate minimum.
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*/
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pciauto_upper_memspc &= ~(0x100000 - 1);
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if (*memsave == pciauto_upper_memspc)
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pciauto_upper_memspc -= 0x00100000;
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_MEMORY_BASE,
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pciauto_upper_memspc >> 16);
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/* Allocate 1MB for pre-fretch */
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_PREF_MEMORY_LIMIT,
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((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
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pciauto_upper_memspc -= 0x100000;
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_PREF_MEMORY_BASE,
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pciauto_upper_memspc >> 16);
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/* Round I/O allocator to 4KB boundary */
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pciauto_upper_iospc &= ~(0x1000 - 1);
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if (*iosave == pciauto_upper_iospc)
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pciauto_upper_iospc -= 0x1000;
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_IO_BASE,
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(pciauto_upper_iospc & 0x0000f000) >> 8);
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early_write_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_IO_BASE_UPPER16,
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pciauto_upper_iospc >> 16);
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/* Enable memory and I/O accesses, enable bus master */
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early_read_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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&cmdstat);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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cmdstat |
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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void __init pciauto_prescan_setup_cardbus_bridge(struct pci_controller *hose,
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int current_bus,
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int pci_devfn,
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int sub_bus,
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int *iosave,
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int *memsave)
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{
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/* Configure bus number registers */
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_PRIMARY_BUS,
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current_bus);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SECONDARY_BUS,
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sub_bus + 1);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SUBORDINATE_BUS,
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0xff);
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/* Round memory allocator to 4KB boundary */
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pciauto_upper_memspc &= ~(0x1000 - 1);
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*memsave = pciauto_upper_memspc;
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/* Round I/O allocator to 4 byte boundary */
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pciauto_upper_iospc &= ~(0x4 - 1);
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*iosave = pciauto_upper_iospc;
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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0x20,
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pciauto_upper_memspc - 1);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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0x30,
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pciauto_upper_iospc - 1);
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}
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void __init pciauto_postscan_setup_cardbus_bridge(struct pci_controller *hose,
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int current_bus,
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int pci_devfn,
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int sub_bus,
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int *iosave,
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int *memsave)
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{
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int cmdstat;
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/*
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* Configure subordinate bus number. The PCI subsystem
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* bus scan will renumber buses (reserving three additional
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* for this PCI<->CardBus bridge for the case where a CardBus
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* adapter contains a P2P or CB2CB bridge.
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*/
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_SUBORDINATE_BUS,
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sub_bus);
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/*
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* Reserve an additional 4MB for mem space and 16KB for
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* I/O space. This should cover any additional space
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* requirement of unusual CardBus devices with
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* additional bridges that can consume more address space.
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*
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* Although pcmcia-cs currently will reprogram bridge
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* windows, the goal is to add an option to leave them
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* alone and use the bridge window ranges as the regions
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* that are searched for free resources upon hot-insertion
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* of a device. This will allow a PCI<->CardBus bridge
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* configured by this routine to happily live behind a
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* P2P bridge in a system.
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*/
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pciauto_upper_memspc -= 0x00400000;
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pciauto_upper_iospc -= 0x00004000;
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/* Round memory allocator to 4KB boundary */
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pciauto_upper_memspc &= ~(0x1000 - 1);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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0x1c,
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pciauto_upper_memspc);
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/* Round I/O allocator to 4 byte boundary */
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pciauto_upper_iospc &= ~(0x4 - 1);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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0x2c,
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pciauto_upper_iospc);
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/* Enable memory and I/O accesses, enable bus master */
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early_read_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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&cmdstat);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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cmdstat |
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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int __init pciauto_bus_scan(struct pci_controller *hose, int current_bus)
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{
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int sub_bus, pci_devfn, pci_class, cmdstat, found_multi = 0;
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unsigned short vid;
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unsigned char header_type;
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/*
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* Fetch our I/O and memory space upper boundaries used
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* to allocated base addresses on this hose.
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*/
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if (current_bus == hose->first_busno) {
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pciauto_upper_iospc = hose->io_space.end + 1;
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pciauto_upper_memspc = hose->mem_space.end + 1;
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}
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sub_bus = current_bus;
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
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/* Skip our host bridge */
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if ( (current_bus == hose->first_busno) && (pci_devfn == 0) )
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continue;
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if (PCI_FUNC(pci_devfn) && !found_multi)
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continue;
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/* If config space read fails from this device, move on */
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if (early_read_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_HEADER_TYPE,
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&header_type))
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continue;
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if (!PCI_FUNC(pci_devfn))
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found_multi = header_type & 0x80;
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early_read_config_word(hose,
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current_bus,
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pci_devfn,
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PCI_VENDOR_ID,
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&vid);
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if (vid != 0xffff) {
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early_read_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_CLASS_REVISION, &pci_class);
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if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
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int iosave, memsave;
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DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
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/* Allocate PCI I/O and/or memory space */
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pciauto_setup_bars(hose,
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current_bus,
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pci_devfn,
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PCI_BASE_ADDRESS_1);
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pciauto_prescan_setup_bridge(hose,
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current_bus,
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pci_devfn,
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sub_bus,
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&iosave,
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&memsave);
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sub_bus = pciauto_bus_scan(hose, sub_bus+1);
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pciauto_postscan_setup_bridge(hose,
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current_bus,
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pci_devfn,
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sub_bus,
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&iosave,
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&memsave);
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} else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
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int iosave, memsave;
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DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
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/* Place CardBus Socket/ExCA registers */
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pciauto_setup_bars(hose,
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current_bus,
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pci_devfn,
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PCI_BASE_ADDRESS_0);
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pciauto_prescan_setup_cardbus_bridge(hose,
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current_bus,
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pci_devfn,
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sub_bus,
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&iosave,
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&memsave);
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sub_bus = pciauto_bus_scan(hose, sub_bus+1);
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pciauto_postscan_setup_cardbus_bridge(hose,
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current_bus,
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pci_devfn,
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sub_bus,
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&iosave,
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&memsave);
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} else {
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if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
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unsigned char prg_iface;
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early_read_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_CLASS_PROG,
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&prg_iface);
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if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
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DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
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continue;
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}
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}
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/* Allocate PCI I/O and/or memory space */
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pciauto_setup_bars(hose,
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current_bus,
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pci_devfn,
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PCI_BASE_ADDRESS_5);
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/*
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* Enable some standard settings
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*/
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early_read_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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&cmdstat);
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early_write_config_dword(hose,
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current_bus,
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pci_devfn,
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PCI_COMMAND,
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cmdstat |
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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early_write_config_byte(hose,
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current_bus,
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pci_devfn,
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PCI_LATENCY_TIMER,
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0x80);
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}
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}
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}
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return sub_bus;
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}
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