298 lines
6.7 KiB
C
298 lines
6.7 KiB
C
/*
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* arch/sh/drivers/dma/dma-sh.c
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*
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* SuperH On-chip DMAC Support
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2005 Andriy Skulysh
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/dreamcast/dma.h>
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#include <asm/signal.h>
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#include <asm/irq.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include "dma-sh.h"
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static inline unsigned int get_dmte_irq(unsigned int chan)
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{
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unsigned int irq = 0;
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/*
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* Normally we could just do DMTE0_IRQ + chan outright, though in the
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* case of the 7751R, the DMTE IRQs for channels > 4 start right above
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* the SCIF
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*/
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if (chan < 4) {
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irq = DMTE0_IRQ + chan;
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} else {
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#ifdef DMTE4_IRQ
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irq = DMTE4_IRQ + chan - 4;
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#endif
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}
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return irq;
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}
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/*
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* We determine the correct shift size based off of the CHCR transmit size
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* for the given channel. Since we know that it will take:
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*
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* info->count >> ts_shift[transmit_size]
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*
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* iterations to complete the transfer.
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*/
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static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
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{
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u32 chcr = ctrl_inl(CHCR[chan->chan]);
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return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
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}
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/*
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* The transfer end interrupt must read the chcr register to end the
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* hardware interrupt active condition.
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* Besides that it needs to waken any waiting process, which should handle
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* setting up the next transfer.
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*/
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static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct dma_channel *chan = (struct dma_channel *)dev_id;
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u32 chcr;
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chcr = ctrl_inl(CHCR[chan->chan]);
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if (!(chcr & CHCR_TE))
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return IRQ_NONE;
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chcr &= ~(CHCR_IE | CHCR_DE);
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ctrl_outl(chcr, CHCR[chan->chan]);
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wake_up(&chan->wait_queue);
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return IRQ_HANDLED;
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}
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static int sh_dmac_request_dma(struct dma_channel *chan)
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{
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char name[32];
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snprintf(name, sizeof(name), "DMAC Transfer End (Channel %d)",
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chan->chan);
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return request_irq(get_dmte_irq(chan->chan), dma_tei,
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SA_INTERRUPT, name, chan);
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}
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static void sh_dmac_free_dma(struct dma_channel *chan)
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{
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free_irq(get_dmte_irq(chan->chan), chan);
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}
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static void
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sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
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{
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if (!chcr)
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chcr = RS_DUAL | CHCR_IE;
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if (chcr & CHCR_IE) {
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chcr &= ~CHCR_IE;
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chan->flags |= DMA_TEI_CAPABLE;
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} else {
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chan->flags &= ~DMA_TEI_CAPABLE;
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}
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ctrl_outl(chcr, CHCR[chan->chan]);
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chan->flags |= DMA_CONFIGURED;
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}
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static void sh_dmac_enable_dma(struct dma_channel *chan)
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{
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int irq;
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u32 chcr;
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chcr = ctrl_inl(CHCR[chan->chan]);
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chcr |= CHCR_DE;
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if (chan->flags & DMA_TEI_CAPABLE)
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chcr |= CHCR_IE;
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ctrl_outl(chcr, CHCR[chan->chan]);
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if (chan->flags & DMA_TEI_CAPABLE) {
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irq = get_dmte_irq(chan->chan);
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enable_irq(irq);
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}
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}
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static void sh_dmac_disable_dma(struct dma_channel *chan)
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{
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int irq;
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u32 chcr;
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if (chan->flags & DMA_TEI_CAPABLE) {
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irq = get_dmte_irq(chan->chan);
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disable_irq(irq);
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}
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chcr = ctrl_inl(CHCR[chan->chan]);
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chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
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ctrl_outl(chcr, CHCR[chan->chan]);
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}
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static int sh_dmac_xfer_dma(struct dma_channel *chan)
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{
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/*
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* If we haven't pre-configured the channel with special flags, use
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* the defaults.
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*/
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if (unlikely(!(chan->flags & DMA_CONFIGURED)))
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sh_dmac_configure_channel(chan, 0);
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sh_dmac_disable_dma(chan);
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/*
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* Single-address mode usage note!
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*
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* It's important that we don't accidentally write any value to SAR/DAR
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* (this includes 0) that hasn't been directly specified by the user if
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* we're in single-address mode.
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*
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* In this case, only one address can be defined, anything else will
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* result in a DMA address error interrupt (at least on the SH-4),
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* which will subsequently halt the transfer.
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*
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* Channel 2 on the Dreamcast is a special case, as this is used for
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* cascading to the PVR2 DMAC. In this case, we still need to write
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* SAR and DAR, regardless of value, in order for cascading to work.
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*/
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if (chan->sar || (mach_is_dreamcast() &&
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chan->chan == PVR2_CASCADE_CHAN))
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ctrl_outl(chan->sar, SAR[chan->chan]);
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if (chan->dar || (mach_is_dreamcast() &&
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chan->chan == PVR2_CASCADE_CHAN))
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ctrl_outl(chan->dar, DAR[chan->chan]);
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ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
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sh_dmac_enable_dma(chan);
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return 0;
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}
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static int sh_dmac_get_dma_residue(struct dma_channel *chan)
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{
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if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
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return 0;
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return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
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}
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#ifdef CONFIG_CPU_SUBTYPE_SH7780
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#define dmaor_read_reg() ctrl_inw(DMAOR)
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#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
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#else
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#define dmaor_read_reg() ctrl_inl(DMAOR)
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#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
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#endif
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static inline int dmaor_reset(void)
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{
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unsigned long dmaor = dmaor_read_reg();
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/* Try to clear the error flags first, incase they are set */
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dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
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dmaor_write_reg(dmaor);
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dmaor |= DMAOR_INIT;
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dmaor_write_reg(dmaor);
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/* See if we got an error again */
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if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
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printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
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return -EINVAL;
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}
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return 0;
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}
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#if defined(CONFIG_CPU_SH4)
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static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
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{
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dmaor_reset();
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disable_irq(irq);
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return IRQ_HANDLED;
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}
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#endif
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static struct dma_ops sh_dmac_ops = {
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.request = sh_dmac_request_dma,
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.free = sh_dmac_free_dma,
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.get_residue = sh_dmac_get_dma_residue,
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.xfer = sh_dmac_xfer_dma,
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.configure = sh_dmac_configure_channel,
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};
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static struct dma_info sh_dmac_info = {
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.name = "sh_dmac",
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.nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
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.ops = &sh_dmac_ops,
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.flags = DMAC_CHANNELS_TEI_CAPABLE,
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};
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static int __init sh_dmac_init(void)
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{
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struct dma_info *info = &sh_dmac_info;
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int i;
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#ifdef CONFIG_CPU_SH4
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make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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i = request_irq(DMAE_IRQ, dma_err, SA_INTERRUPT, "DMAC Address Error", 0);
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if (i < 0)
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return i;
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#endif
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for (i = 0; i < info->nr_channels; i++) {
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int irq = get_dmte_irq(i);
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make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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}
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/*
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* Initialize DMAOR, and clean up any error flags that may have
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* been set.
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*/
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i = dmaor_reset();
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if (i < 0)
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return i;
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return register_dmac(info);
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}
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static void __exit sh_dmac_exit(void)
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{
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#ifdef CONFIG_CPU_SH4
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free_irq(DMAE_IRQ, 0);
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#endif
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unregister_dmac(&sh_dmac_info);
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}
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subsys_initcall(sh_dmac_init);
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module_exit(sh_dmac_exit);
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MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
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MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
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MODULE_LICENSE("GPL");
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