175 lines
4.4 KiB
C
175 lines
4.4 KiB
C
/*
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* Board setup routines for the SBS PalomarIV.
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*
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* Author: Dan Cox
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*
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* 2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/time.h>
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#include <linux/irq.h>
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#include <linux/kdev_t.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <asm/io.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/machdep.h>
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#include <syslib/cpc700.h>
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#include "pal4.h"
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extern void pal4_find_bridges(void);
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unsigned int cpc700_irq_assigns[][2] = {
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{1, 1}, /* IRQ 0: ECC correctable error */
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{1, 1}, /* IRQ 1: PCI write to memory range */
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{0, 1}, /* IRQ 2: PCI write to command register */
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{0, 1}, /* IRQ 3: UART 0 */
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{0, 1}, /* IRQ 4: UART 1 */
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{0, 1}, /* IRQ 5: ICC 0 */
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{0, 1}, /* IRQ 6: ICC 1 */
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{0, 1}, /* IRQ 7: GPT compare 0 */
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{0, 1}, /* IRQ 8: GPT compare 1 */
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{0, 1}, /* IRQ 9: GPT compare 2 */
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{0, 1}, /* IRQ 10: GPT compare 3 */
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{0, 1}, /* IRQ 11: GPT compare 4 */
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{0, 1}, /* IRQ 12: GPT capture 0 */
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{0, 1}, /* IRQ 13: GPT capture 1 */
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{0, 1}, /* IRQ 14: GPT capture 2 */
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{0, 1}, /* IRQ 15: GPT capture 3 */
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{0, 1}, /* IRQ 16: GPT capture 4 */
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{0, 0}, /* IRQ 17: reserved */
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{0, 0}, /* IRQ 18: reserved */
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{0, 0}, /* IRQ 19: reserved */
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{0, 0}, /* IRQ 20: reserved */
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{0, 1}, /* IRQ 21: Ethernet */
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{0, 0}, /* IRQ 22: reserved */
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{0, 0}, /* IRQ 23: reserved */
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{0, 0}, /* IRQ 24: resreved */
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{0, 0}, /* IRQ 25: reserved */
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{0, 0}, /* IRQ 26: reserved */
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{0, 0}, /* IRQ 27: reserved */
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{0, 0}, /* IRQ 28: reserved */
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{0, 0}, /* IRQ 29: reserved */
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{0, 0}, /* IRQ 30: reserved */
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{0, 0}, /* IRQ 31: reserved */
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};
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static int
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pal4_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "board\t\t: SBS Palomar IV\n");
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return 0;
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}
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static void
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pal4_restart(char *cmd)
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{
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local_irq_disable();
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__asm__ __volatile__("lis 3,0xfff0\n \
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ori 3,3,0x100\n \
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mtspr 26,3\n \
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li 3,0\n \
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mtspr 27,3\n \
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rfi");
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for(;;);
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}
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static void
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pal4_power_off(void)
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{
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local_irq_disable();
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for(;;);
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}
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static void
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pal4_halt(void)
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{
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pal4_power_off();
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}
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TODC_ALLOC();
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static void __init
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pal4_setup_arch(void)
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{
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unsigned long l2;
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TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
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ioremap(PAL4_NVRAM, PAL4_NVRAM_SIZE), 8);
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pal4_find_bridges();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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ROOT_DEV = Root_NFS;
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/* The L2 gets disabled in the bootloader, but all the proper
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bits should be present from the fw, so just re-enable it */
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l2 = _get_L2CR();
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if (!(l2 & L2CR_L2E)) {
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/* presume that it was initially set if the size is
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still present. */
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if (l2 ^ L2CR_L2SIZ_MASK)
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_set_L2CR(l2 | L2CR_L2E);
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else
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printk("L2 not set by firmware; left disabled.\n");
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}
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}
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static void __init
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pal4_map_io(void)
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{
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io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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isa_io_base = 0 /*PAL4_ISA_IO_BASE*/;
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pci_dram_offset = 0 /*PAL4_PCI_SYS_MEM_BASE*/;
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ppc_md.setup_arch = pal4_setup_arch;
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ppc_md.show_cpuinfo = pal4_show_cpuinfo;
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ppc_md.setup_io_mappings = pal4_map_io;
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ppc_md.init_IRQ = cpc700_init_IRQ;
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ppc_md.get_irq = cpc700_get_irq;
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ppc_md.restart = pal4_restart;
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ppc_md.halt = pal4_halt;
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ppc_md.power_off = pal4_power_off;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.calibrate_decr = todc_calibrate_decr;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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}
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